From: Tim Northover Date: Fri, 18 Jul 2014 13:01:43 +0000 (+0000) Subject: NVPTX: support fpext/fptrunc to and from f16. X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=9e108a0e3a21d18eb4768371121c830bac0c2198;p=platform%2Fupstream%2Fllvm.git NVPTX: support fpext/fptrunc to and from f16. llvm-svn: 213377 --- diff --git a/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp b/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp index 645a9bb..05bad16 100644 --- a/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp +++ b/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp @@ -203,8 +203,11 @@ NVPTXTargetLowering::NVPTXTargetLowering(NVPTXTargetMachine &TM) setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom); // Turn FP extload into load/fextend + setLoadExtAction(ISD::EXTLOAD, MVT::f16, Expand); setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand); // Turn FP truncstore into trunc + store. + setTruncStoreAction(MVT::f32, MVT::f16, Expand); + setTruncStoreAction(MVT::f64, MVT::f16, Expand); setTruncStoreAction(MVT::f64, MVT::f32, Expand); // PTX does not support load / store predicate registers diff --git a/llvm/test/CodeGen/NVPTX/half.ll b/llvm/test/CodeGen/NVPTX/half.ll index ba18dc3..aa08cc7 100644 --- a/llvm/test/CodeGen/NVPTX/half.ll +++ b/llvm/test/CodeGen/NVPTX/half.ll @@ -28,3 +28,43 @@ define void @test_bitcast_to_half(half addrspace(1)* %out, i16 addrspace(1)* %in store half %val_fp, half addrspace(1)* %out ret void } + +define void @test_extend32(half addrspace(1)* %in, float addrspace(1)* %out) { +; CHECK-LABEL: @test_extend32 +; CHECK: cvt.f32.f16 + + %val16 = load half addrspace(1)* %in + %val32 = fpext half %val16 to float + store float %val32, float addrspace(1)* %out + ret void +} + +define void @test_extend64(half addrspace(1)* %in, double addrspace(1)* %out) { +; CHECK-LABEL: @test_extend64 +; CHECK: cvt.f64.f16 + + %val16 = load half addrspace(1)* %in + %val64 = fpext half %val16 to double + store double %val64, double addrspace(1)* %out + ret void +} + +define void @test_trunc32(float addrspace(1)* %in, half addrspace(1)* %out) { +; CHECK-LABEL: test_trunc32 +; CHECK: cvt.rn.f16.f32 + + %val32 = load float addrspace(1)* %in + %val16 = fptrunc float %val32 to half + store half %val16, half addrspace(1)* %out + ret void +} + +define void @test_trunc64(double addrspace(1)* %in, half addrspace(1)* %out) { +; CHECK-LABEL: @test_trunc64 +; CHECK: cvt.rn.f16.f64 + + %val32 = load double addrspace(1)* %in + %val16 = fptrunc double %val32 to half + store half %val16, half addrspace(1)* %out + ret void +}