From: Marek Olšák <marek.olsak@amd.com>
Date: Mon, 15 May 2023 20:10:34 +0000 (-0400)
Subject: radeonsi: don't enable WGP_MODE because of high cost of workgroup mem coherency
X-Git-Tag: upstream/23.3.3~8027
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=9d7eab2ab17b3ffcf8c965c9e7cf89ff1bf2b7ac;p=platform%2Fupstream%2Fmesa.git

radeonsi: don't enable WGP_MODE because of high cost of workgroup mem coherency

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23216>
---

diff --git a/src/gallium/drivers/radeonsi/si_compute.c b/src/gallium/drivers/radeonsi/si_compute.c
index 282e3b9..3f1a863 100644
--- a/src/gallium/drivers/radeonsi/si_compute.c
+++ b/src/gallium/drivers/radeonsi/si_compute.c
@@ -182,7 +182,6 @@ static void si_create_compute_state_async(void *job, void *gdata, int thread_ind
                                               sscreen->info.wave64_vgpr_alloc_granularity == 8) ? 8 : 4)) |
                              S_00B848_DX10_CLAMP(1) |
                              S_00B848_MEM_ORDERED(si_shader_mem_ordered(shader)) |
-                             S_00B848_WGP_MODE(sscreen->info.gfx_level >= GFX10) |
                              S_00B848_FLOAT_MODE(shader->config.float_mode);
 
       if (sscreen->info.gfx_level < GFX10) {
diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.cpp b/src/gallium/drivers/radeonsi/si_state_shaders.cpp
index 72bf73e..f4b548c 100644
--- a/src/gallium/drivers/radeonsi/si_state_shaders.cpp
+++ b/src/gallium/drivers/radeonsi/si_state_shaders.cpp
@@ -740,7 +740,6 @@ static void si_shader_hs(struct si_screen *sscreen, struct si_shader *shader)
                   S_00B428_SGPRS(si_shader_encode_sgprs(shader)) |
                   S_00B428_DX10_CLAMP(1) |
                   S_00B428_MEM_ORDERED(si_shader_mem_ordered(shader)) |
-                  S_00B428_WGP_MODE(sscreen->info.gfx_level >= GFX10) |
                   S_00B428_FLOAT_MODE(shader->config.float_mode) |
                   S_00B428_LS_VGPR_COMP_CNT(sscreen->info.gfx_level >= GFX9 ?
                                             si_get_vs_vgpr_comp_cnt(sscreen, shader, false) : 0));
@@ -1079,7 +1078,6 @@ static void si_shader_gs(struct si_screen *sscreen, struct si_shader *shader)
                        S_00B228_SGPRS(si_shader_encode_sgprs(shader)) |
                        S_00B228_DX10_CLAMP(1) |
                        S_00B228_MEM_ORDERED(si_shader_mem_ordered(shader)) |
-                       S_00B228_WGP_MODE(sscreen->info.gfx_level >= GFX10) |
                        S_00B228_FLOAT_MODE(shader->config.float_mode) |
                        S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt);
       uint32_t rsrc2 = S_00B22C_USER_SGPR(num_user_sgprs) |
@@ -1374,9 +1372,6 @@ static void gfx10_shader_ngg(struct si_screen *sscreen, struct si_shader *shader
                   S_00B228_FLOAT_MODE(shader->config.float_mode) |
                   S_00B228_DX10_CLAMP(1) |
                   S_00B228_MEM_ORDERED(si_shader_mem_ordered(shader)) |
-                  /* Disable the WGP mode on gfx10.3 because it can hang. (it happened on VanGogh)
-                   * Let's disable it on all chips that disable exactly 1 CU per SA for GS. */
-                  S_00B228_WGP_MODE(sscreen->info.gfx_level == GFX10) |
                   S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt));
    si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
                   S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0) |