From: Craig Topper <craig.topper@sifive.com>
Date: Sat, 14 Nov 2020 07:29:05 +0000 (-0800)
Subject: [RISCV] Add test cases for fsrw/fslw that don't sign extend the result. NFC
X-Git-Tag: llvmorg-13-init~6088
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=9d62ef6bc99f1d181fa4e30314c5b24fbf612883;p=platform%2Fupstream%2Fllvm.git

[RISCV] Add test cases for fsrw/fslw that don't sign extend the result. NFC

These currently fail to select fsrw/fslw.
---

diff --git a/llvm/test/CodeGen/RISCV/rv64Zbt.ll b/llvm/test/CodeGen/RISCV/rv64Zbt.ll
index 8b7b938..d88a2ad 100644
--- a/llvm/test/CodeGen/RISCV/rv64Zbt.ll
+++ b/llvm/test/CodeGen/RISCV/rv64Zbt.ll
@@ -133,6 +133,43 @@ define signext i32 @fshl_i32(i32 signext %a, i32 signext %b, i32 signext %c) nou
   ret i32 %1
 }
 
+; Similar to fshl_i32 but result is not sign extended.
+; FIXME: This should use fslw
+define void @fshl_i32_nosext(i32 signext %a, i32 signext %b, i32 signext %c, i32* %x) nounwind {
+; RV64I-LABEL: fshl_i32_nosext:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    slli a0, a0, 32
+; RV64I-NEXT:    slli a1, a1, 32
+; RV64I-NEXT:    srli a1, a1, 32
+; RV64I-NEXT:    or a0, a0, a1
+; RV64I-NEXT:    andi a1, a2, 31
+; RV64I-NEXT:    sll a0, a0, a1
+; RV64I-NEXT:    srli a0, a0, 32
+; RV64I-NEXT:    sw a0, 0(a3)
+; RV64I-NEXT:    ret
+;
+; RV64IB-LABEL: fshl_i32_nosext:
+; RV64IB:       # %bb.0:
+; RV64IB-NEXT:    slli a1, a1, 32
+; RV64IB-NEXT:    andi a2, a2, 31
+; RV64IB-NEXT:    andi a2, a2, 63
+; RV64IB-NEXT:    fsl a0, a0, a1, a2
+; RV64IB-NEXT:    sw a0, 0(a3)
+; RV64IB-NEXT:    ret
+;
+; RV64IBT-LABEL: fshl_i32_nosext:
+; RV64IBT:       # %bb.0:
+; RV64IBT-NEXT:    slli a1, a1, 32
+; RV64IBT-NEXT:    andi a2, a2, 31
+; RV64IBT-NEXT:    andi a2, a2, 63
+; RV64IBT-NEXT:    fsl a0, a0, a1, a2
+; RV64IBT-NEXT:    sw a0, 0(a3)
+; RV64IBT-NEXT:    ret
+  %1 = tail call i32 @llvm.fshl.i32(i32 %a, i32 %b, i32 %c)
+  store i32 %1, i32* %x
+  ret void
+}
+
 declare i64 @llvm.fshl.i64(i64, i64, i64)
 
 define i64 @fshl_i64(i64 %a, i64 %b, i64 %c) nounwind {
@@ -189,6 +226,42 @@ define signext i32 @fshr_i32(i32 signext %a, i32 signext %b, i32 signext %c) nou
   ret i32 %1
 }
 
+; Similar to fshr_i32 but result is not sign extended.
+; FIXME: This should use fsrw
+define void @fshr_i32_nosext(i32 signext %a, i32 signext %b, i32 signext %c, i32* %x) nounwind {
+; RV64I-LABEL: fshr_i32_nosext:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    slli a0, a0, 32
+; RV64I-NEXT:    slli a1, a1, 32
+; RV64I-NEXT:    srli a1, a1, 32
+; RV64I-NEXT:    or a0, a0, a1
+; RV64I-NEXT:    andi a1, a2, 31
+; RV64I-NEXT:    srl a0, a0, a1
+; RV64I-NEXT:    sw a0, 0(a3)
+; RV64I-NEXT:    ret
+;
+; RV64IB-LABEL: fshr_i32_nosext:
+; RV64IB:       # %bb.0:
+; RV64IB-NEXT:    slli a1, a1, 32
+; RV64IB-NEXT:    ori a2, a2, 32
+; RV64IB-NEXT:    andi a2, a2, 63
+; RV64IB-NEXT:    fsr a0, a1, a0, a2
+; RV64IB-NEXT:    sw a0, 0(a3)
+; RV64IB-NEXT:    ret
+;
+; RV64IBT-LABEL: fshr_i32_nosext:
+; RV64IBT:       # %bb.0:
+; RV64IBT-NEXT:    slli a1, a1, 32
+; RV64IBT-NEXT:    ori a2, a2, 32
+; RV64IBT-NEXT:    andi a2, a2, 63
+; RV64IBT-NEXT:    fsr a0, a1, a0, a2
+; RV64IBT-NEXT:    sw a0, 0(a3)
+; RV64IBT-NEXT:    ret
+  %1 = tail call i32 @llvm.fshr.i32(i32 %a, i32 %b, i32 %c)
+  store i32 %1, i32* %x
+  ret void
+}
+
 declare i64 @llvm.fshr.i64(i64, i64, i64)
 
 define i64 @fshr_i64(i64 %a, i64 %b, i64 %c) nounwind {
@@ -238,6 +311,35 @@ define signext i32 @fshri_i32(i32 signext %a, i32 signext %b) nounwind {
   ret i32 %1
 }
 
+; Similar to fshr_i32 but result is not sign extended.
+; FIXME: This should use fsriw
+define void @fshri_i32_nosext(i32 signext %a, i32 signext %b, i32* %x) nounwind {
+; RV64I-LABEL: fshri_i32_nosext:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    srliw a1, a1, 5
+; RV64I-NEXT:    slli a0, a0, 27
+; RV64I-NEXT:    or a0, a0, a1
+; RV64I-NEXT:    sw a0, 0(a2)
+; RV64I-NEXT:    ret
+;
+; RV64IB-LABEL: fshri_i32_nosext:
+; RV64IB:       # %bb.0:
+; RV64IB-NEXT:    slli a1, a1, 32
+; RV64IB-NEXT:    fsri a0, a1, a0, 37
+; RV64IB-NEXT:    sw a0, 0(a2)
+; RV64IB-NEXT:    ret
+;
+; RV64IBT-LABEL: fshri_i32_nosext:
+; RV64IBT:       # %bb.0:
+; RV64IBT-NEXT:    slli a1, a1, 32
+; RV64IBT-NEXT:    fsri a0, a1, a0, 37
+; RV64IBT-NEXT:    sw a0, 0(a2)
+; RV64IBT-NEXT:    ret
+  %1 = tail call i32 @llvm.fshr.i32(i32 %a, i32 %b, i32 5)
+  store i32 %1, i32* %x
+  ret void
+}
+
 define i64 @fshri_i64(i64 %a, i64 %b) nounwind {
 ; RV64I-LABEL: fshri_i64:
 ; RV64I:       # %bb.0:
@@ -281,6 +383,35 @@ define signext i32 @fshli_i32(i32 signext %a, i32 signext %b) nounwind {
   ret i32 %1
 }
 
+; Similar to fshl_i32 but result is not sign extended.
+; FIXME: This should use fsriw
+define void @fshli_i32_nosext(i32 signext %a, i32 signext %b, i32* %x) nounwind {
+; RV64I-LABEL: fshli_i32_nosext:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    srliw a1, a1, 27
+; RV64I-NEXT:    slli a0, a0, 5
+; RV64I-NEXT:    or a0, a0, a1
+; RV64I-NEXT:    sw a0, 0(a2)
+; RV64I-NEXT:    ret
+;
+; RV64IB-LABEL: fshli_i32_nosext:
+; RV64IB:       # %bb.0:
+; RV64IB-NEXT:    slli a1, a1, 32
+; RV64IB-NEXT:    fsri a0, a1, a0, 59
+; RV64IB-NEXT:    sw a0, 0(a2)
+; RV64IB-NEXT:    ret
+;
+; RV64IBT-LABEL: fshli_i32_nosext:
+; RV64IBT:       # %bb.0:
+; RV64IBT-NEXT:    slli a1, a1, 32
+; RV64IBT-NEXT:    fsri a0, a1, a0, 59
+; RV64IBT-NEXT:    sw a0, 0(a2)
+; RV64IBT-NEXT:    ret
+  %1 = tail call i32 @llvm.fshl.i32(i32 %a, i32 %b, i32 5)
+  store i32 %1, i32* %x
+  ret void
+}
+
 define i64 @fshli_i64(i64 %a, i64 %b) nounwind {
 ; RV64I-LABEL: fshli_i64:
 ; RV64I:       # %bb.0: