From: Dinh Nguyen Date: Tue, 13 Jul 2021 14:46:19 +0000 (-0500) Subject: clk: socfpga: agilex: fix the parents of the psi_ref_clk X-Git-Tag: accepted/tizen/unified/20230118.172025~6390^2~5^3~2 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=9d563236cca43fc4fe190b3be173444bd48e2a3b;p=platform%2Fkernel%2Flinux-rpi.git clk: socfpga: agilex: fix the parents of the psi_ref_clk The psi_ref_clk comes from the C2 node of the main_pll and periph_pll, not the C3. Fixes: 80c6b7a0894f ("clk: socfpga: agilex: add clock driver for the Agilex platform") Cc: stable@vger.kernel.org Signed-off-by: Kris Chaplin Signed-off-by: Dinh Nguyen Link: https://lore.kernel.org/r/20210713144621.605140-1-dinguyen@kernel.org Signed-off-by: Stephen Boyd --- diff --git a/drivers/clk/socfpga/clk-agilex.c b/drivers/clk/socfpga/clk-agilex.c index 1cb21ea..9dffe9b 100644 --- a/drivers/clk/socfpga/clk-agilex.c +++ b/drivers/clk/socfpga/clk-agilex.c @@ -107,10 +107,10 @@ static const struct clk_parent_data gpio_db_free_mux[] = { }; static const struct clk_parent_data psi_ref_free_mux[] = { - { .fw_name = "main_pll_c3", - .name = "main_pll_c3", }, - { .fw_name = "peri_pll_c3", - .name = "peri_pll_c3", }, + { .fw_name = "main_pll_c2", + .name = "main_pll_c2", }, + { .fw_name = "peri_pll_c2", + .name = "peri_pll_c2", }, { .fw_name = "osc1", .name = "osc1", }, { .fw_name = "cb-intosc-hs-div2-clk",