From: Richard Osborne Date: Mon, 21 Jan 2013 20:44:17 +0000 (+0000) Subject: Add instruction encodings / disassembly support for u6 / lu6 instructions. X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=9d3ec06ef801942db816334da9969addf9fb580a;p=platform%2Fupstream%2Fllvm.git Add instruction encodings / disassembly support for u6 / lu6 instructions. llvm-svn: 173086 --- diff --git a/llvm/lib/Target/XCore/XCoreInstrFormats.td b/llvm/lib/Target/XCore/XCoreInstrFormats.td index fa5c0a2..0e0aab9 100644 --- a/llvm/lib/Target/XCore/XCoreInstrFormats.td +++ b/llvm/lib/Target/XCore/XCoreInstrFormats.td @@ -107,12 +107,22 @@ class _FLRU6 opc, dag outs, dag ins, string asmstr, list pattern> let Inst{9-0} = b{15-6}; } -class _FU6 pattern> +class _FU6 opc, dag outs, dag ins, string asmstr, list pattern> : InstXCore<2, outs, ins, asmstr, pattern> { + bits<6> a; + + let Inst{15-6} = opc; + let Inst{5-0} = a; } -class _FLU6 pattern> +class _FLU6 opc, dag outs, dag ins, string asmstr, list pattern> : InstXCore<4, outs, ins, asmstr, pattern> { + bits<16> a; + + let Inst{31-22} = opc; + let Inst{21-16} = a{5-0}; + let Inst{15-10} = 0b111100; + let Inst{9-0} = a{15-6}; } class _FU10 pattern> diff --git a/llvm/lib/Target/XCore/XCoreInstrInfo.td b/llvm/lib/Target/XCore/XCoreInstrInfo.td index 5ca2b0f..a3e16be 100644 --- a/llvm/lib/Target/XCore/XCoreInstrInfo.td +++ b/llvm/lib/Target/XCore/XCoreInstrInfo.td @@ -288,36 +288,23 @@ multiclass FRU6_LRU6_cp opc, string OpcStr> { } // U6 -multiclass FU6_LU6 { - def _u6: _FU6< - (outs), (ins i32imm:$b), - !strconcat(OpcStr, " $b"), - [(OpNode immU6:$b)]>; - def _lu6: _FLU6< - (outs), (ins i32imm:$b), - !strconcat(OpcStr, " $b"), - [(OpNode immU16:$b)]>; +multiclass FU6_LU6 opc, string OpcStr, SDNode OpNode> { + def _u6: _FU6; + def _lu6: _FLU6; } -multiclass FU6_LU6_int { - def _u6: _FU6< - (outs), (ins i32imm:$b), - !strconcat(OpcStr, " $b"), - [(Int immU6:$b)]>; - def _lu6: _FLU6< - (outs), (ins i32imm:$b), - !strconcat(OpcStr, " $b"), - [(Int immU16:$b)]>; + +multiclass FU6_LU6_int opc, string OpcStr, Intrinsic Int> { + def _u6: _FU6; + def _lu6: _FLU6; } -multiclass FU6_LU6_np { - def _u6: _FU6< - (outs), (ins i32imm:$b), - !strconcat(OpcStr, " $b"), - []>; - def _lu6: _FLU6< - (outs), (ins i32imm:$b), - !strconcat(OpcStr, " $b"), - []>; +multiclass FU6_LU6_np opc, string OpcStr> { + def _u6: _FU6; + def _lu6: _FLU6; } // U10 @@ -628,60 +615,46 @@ defm BRBF: FRU6_LRU6_backwards_branch<0b011111, "bf">; // U6 let Defs = [SP], Uses = [SP] in { let neverHasSideEffects = 1 in -defm EXTSP : FU6_LU6_np<"extsp">; +defm EXTSP : FU6_LU6_np<0b0111011110, "extsp">; let mayStore = 1 in -defm ENTSP : FU6_LU6_np<"entsp">; +defm ENTSP : FU6_LU6_np<0b0111011101, "entsp">; let isReturn = 1, isTerminator = 1, mayLoad = 1, isBarrier = 1 in { -defm RETSP : FU6_LU6<"retsp", XCoreRetsp>; +defm RETSP : FU6_LU6<0b0111011111, "retsp", XCoreRetsp>; } } // TODO extdp, kentsp, krestsp, blat // getsr, kalli let isBranch = 1, isTerminator = 1, isBarrier = 1 in { -def BRBU_u6 : _FU6< - (outs), - (ins brtarget:$target), - "bu $target", - []>; +def BRBU_u6 : _FU6<0b0111011100, (outs), (ins brtarget:$a), "bu -$a", []>; -def BRBU_lu6 : _FLU6< - (outs), - (ins brtarget:$target), - "bu $target", - []>; +def BRBU_lu6 : _FLU6<0b0111011100, (outs), (ins brtarget:$a), "bu -$a", []>; -def BRFU_u6 : _FU6< - (outs), - (ins brtarget:$target), - "bu $target", - []>; +def BRFU_u6 : _FU6<0b0111001100, (outs), (ins brtarget:$a), "bu $a", []>; -def BRFU_lu6 : _FLU6< - (outs), - (ins brtarget:$target), - "bu $target", - []>; +def BRFU_lu6 : _FLU6<0b0111001100, (outs), (ins brtarget:$a), "bu $a", []>; } //let Uses = [CP] in ... let Defs = [R11], neverHasSideEffects = 1, isReMaterializable = 1 in -def LDAWCP_u6: _FU6<(outs), (ins MEMii:$a), "ldaw r11, cp[$a]", []>; +def LDAWCP_u6: _FU6<0b0111111101, (outs), (ins MEMii:$a), "ldaw r11, cp[$a]", + []>; let Defs = [R11], isReMaterializable = 1 in -def LDAWCP_lu6: _FLU6<(outs), (ins MEMii:$a), "ldaw r11, cp[$a]", +def LDAWCP_lu6: _FLU6<0b0111111101, (outs), (ins MEMii:$a), "ldaw r11, cp[$a]", [(set R11, ADDRcpii:$a)]>; -defm SETSR : FU6_LU6_int<"setsr", int_xcore_setsr>; +defm SETSR : FU6_LU6_int<0b0111101101, "setsr", int_xcore_setsr>; -defm CLRSR : FU6_LU6_int<"clrsr", int_xcore_clrsr>; +defm CLRSR : FU6_LU6_int<0b0111101100, "clrsr", int_xcore_clrsr>; // setsr may cause a branch if it is used to enable events. clrsr may // branch if it is executed while events are enabled. -let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1 in { -defm SETSR_branch : FU6_LU6_np<"setsr">; -defm CLRSR_branch : FU6_LU6_np<"clrsr">; +let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1, + isCodeGenOnly = 1 in { +defm SETSR_branch : FU6_LU6_np<0b0111101101, "setsr">; +defm CLRSR_branch : FU6_LU6_np<0b0111101100, "clrsr">; } // U10 diff --git a/llvm/test/MC/Disassembler/XCore/xcore.txt b/llvm/test/MC/Disassembler/XCore/xcore.txt index 507c762..62e3ef6 100644 --- a/llvm/test/MC/Disassembler/XCore/xcore.txt +++ b/llvm/test/MC/Disassembler/XCore/xcore.txt @@ -392,3 +392,53 @@ # CHECK: stw r0, sp[8761] 0x88 0xf0 0x39 0x54 + +# u6 / lu6 instructions + +# CHECK: bu -20 +0x14 0x77 + +# CHECK: bu -1000 +0x0f 0xf0 0x28 0x77 + +# CHECK: bu 24 +0x18 0x73 + +# CHECK: bu 2231 +0x22 0xf0 0x37 0x73 + +# CHECK: extsp 9 +0x89 0x77 + +# CHECK: extsp 5721 +0x59 0xf0 0x99 0x77 + +# CHECK: clrsr 60 +0x3c 0x7b + +# CHECK: clrsr 64391 +0xee 0xf3 0x07 0x7b + +# CHECK: entsp 1 +0x41 0x77 + +# CHECK: entsp 70 +0x01 0xf0 0x46 0x77 + +# CHECK: ldaw r11, cp[5] +0x45 0x7f + +# CHECK: ldaw r11, cp[33000] +0x03 0xf2 0x68 0x7f + +# CHECK: retsp 40 +0xe8 0x77 + +# CHECK: retsp 52010 +0x2c 0xf3 0xea 0x77 + +# CHECK: setsr 42 +0x6a 0x7b + +# CHECK: setsr 21863 +0x55 0xf1 0x67 0x7b