From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Date: Fri, 16 Sep 2022 06:33:01 +0000 (+0300)
Subject: freedreno/registers: update hdmi registers to add more 8x74 regs
X-Git-Tag: upstream/22.3.5~2921
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=9d3a5c916c5c5b1b015a4b56bf27a7707a290118;p=platform%2Fupstream%2Fmesa.git

freedreno/registers: update hdmi registers to add more 8x74 regs

Define more HDMI PHY/PLL registers used on msm8x74/apq8084 platforms.
Register names are defined in clock-mdss-8974.c (msm-3.10).

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18629>
---

diff --git a/src/freedreno/registers/hdmi/hdmi.xml b/src/freedreno/registers/hdmi/hdmi.xml
index af22313..7555d02 100644
--- a/src/freedreno/registers/hdmi/hdmi.xml
+++ b/src/freedreno/registers/hdmi/hdmi.xml
@@ -643,13 +643,23 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
 	 -->
 	<reg32 offset="0x00000" name="ANA_CFG0"/>
 	<reg32 offset="0x00004" name="ANA_CFG1"/>
+	<reg32 offset="0x00008" name="ANA_CFG2"/>
+	<reg32 offset="0x0000c" name="ANA_CFG3"/>
 	<reg32 offset="0x00010" name="PD_CTRL0"/>
 	<reg32 offset="0x00014" name="PD_CTRL1"/>
+	<reg32 offset="0x00018" name="GLB_CFG"/>
+	<reg32 offset="0x0001c" name="DCC_CFG0"/>
+	<reg32 offset="0x00020" name="DCC_CFG1"/>
+	<reg32 offset="0x00024" name="TXCAL_CFG0"/>
+	<reg32 offset="0x00028" name="TXCAL_CFG1"/>
+	<reg32 offset="0x0002c" name="TXCAL_CFG2"/>
+	<reg32 offset="0x00030" name="TXCAL_CFG3"/>
 	<reg32 offset="0x00034" name="BIST_CFG0"/>
 	<reg32 offset="0x0003c" name="BIST_PATN0"/>
 	<reg32 offset="0x00040" name="BIST_PATN1"/>
 	<reg32 offset="0x00044" name="BIST_PATN2"/>
 	<reg32 offset="0x00048" name="BIST_PATN3"/>
+	<reg32 offset="0x0005c" name="STATUS"/>
 </domain>
 
 <domain name="HDMI_28nm_PHY_PLL" width="32">
@@ -701,6 +711,7 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
 	<reg32 offset="0x00098" name="CAL_CFG11"/>
 	<reg32 offset="0x0009C" name="EFUSE_CFG"/>
 	<reg32 offset="0x000A0" name="DEBUG_BUS_SEL"/>
+	<reg32 offset="0x000C0" name="STATUS"/>
 </domain>
 
 <domain name="HDMI_8996_PHY" width="32">