From: Alexander Ivchenko Date: Fri, 31 Aug 2018 11:26:51 +0000 (+0000) Subject: [GlobalISel][X86] Add the support for G_FPTRUNC X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=9d053074a1ad84a238de9bb434e2693b43715659;p=platform%2Fupstream%2Fllvm.git [GlobalISel][X86] Add the support for G_FPTRUNC Differential Revision: https://reviews.llvm.org/D49855 llvm-svn: 341202 --- diff --git a/llvm/lib/Target/X86/X86LegalizerInfo.cpp b/llvm/lib/Target/X86/X86LegalizerInfo.cpp index 2b747f7..4e64e8e 100644 --- a/llvm/lib/Target/X86/X86LegalizerInfo.cpp +++ b/llvm/lib/Target/X86/X86LegalizerInfo.cpp @@ -305,6 +305,9 @@ void X86LegalizerInfo::setLegalizerInfoSSE2() { setAction({G_FPEXT, s64}, Legal); setAction({G_FPEXT, 1, s32}, Legal); + setAction({G_FPTRUNC, s32}, Legal); + setAction({G_FPTRUNC, 1, s64}, Legal); + // Constants setAction({TargetOpcode::G_FCONSTANT, s64}, Legal); diff --git a/llvm/lib/Target/X86/X86RegisterBankInfo.cpp b/llvm/lib/Target/X86/X86RegisterBankInfo.cpp index 47dff31..3552919 100644 --- a/llvm/lib/Target/X86/X86RegisterBankInfo.cpp +++ b/llvm/lib/Target/X86/X86RegisterBankInfo.cpp @@ -194,6 +194,7 @@ X86RegisterBankInfo::getInstrMapping(const MachineInstr &MI) const { switch (Opc) { case TargetOpcode::G_FPEXT: + case TargetOpcode::G_FPTRUNC: case TargetOpcode::G_FCONSTANT: // Instruction having only floating-point operands (all scalars in VECRReg) getInstrPartialMappingIdxs(MI, MRI, /* isFP */ true, OpRegBankIdx); diff --git a/llvm/test/CodeGen/X86/GlobalISel/legalize-fptrunc-scalar.mir b/llvm/test/CodeGen/X86/GlobalISel/legalize-fptrunc-scalar.mir new file mode 100644 index 0000000..fbe139f --- /dev/null +++ b/llvm/test/CodeGen/X86/GlobalISel/legalize-fptrunc-scalar.mir @@ -0,0 +1,39 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=x86_64-linux-gnu -run-pass=legalizer %s -o - | FileCheck %s --check-prefix=ALL +--- | + + define float @test_fptrunc(double %in) { + %res = fptrunc double %in to float + ret float %res + } + +... +--- +name: test_fptrunc +alignment: 4 +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } + - { id: 3, class: _ } +body: | + bb.1 (%ir-block.0): + liveins: $xmm0 + + ; ALL-LABEL: name: test_fptrunc + ; ALL: liveins: $xmm0 + ; ALL: [[COPY:%[0-9]+]]:_(s128) = COPY $xmm0 + ; ALL: [[TRUNC:%[0-9]+]]:_(s64) = G_TRUNC [[COPY]](s128) + ; ALL: [[FPTRUNC:%[0-9]+]]:_(s32) = G_FPTRUNC [[TRUNC]](s64) + ; ALL: [[ANYEXT:%[0-9]+]]:_(s128) = G_ANYEXT [[FPTRUNC]](s32) + ; ALL: $xmm0 = COPY [[ANYEXT]](s128) + ; ALL: RET 0, implicit $xmm0 + %1:_(s128) = COPY $xmm0 + %0:_(s64) = G_TRUNC %1(s128) + %2:_(s32) = G_FPTRUNC %0(s64) + %3:_(s128) = G_ANYEXT %2(s32) + $xmm0 = COPY %3(s128) + RET 0, implicit $xmm0 + +... diff --git a/llvm/test/CodeGen/X86/GlobalISel/regbankselect-X86_64.mir b/llvm/test/CodeGen/X86/GlobalISel/regbankselect-X86_64.mir index ab46f2f..2b73058 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/regbankselect-X86_64.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/regbankselect-X86_64.mir @@ -238,6 +238,12 @@ ret double %conv } + define float @test_fptrunc(double %a) { + entry: + %conv = fptrunc double %a to float + ret float %conv + } + define void @test_fconstant() { ret void } @@ -2013,6 +2019,44 @@ body: | ... --- +name: test_fptrunc +alignment: 4 +legalized: true +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } + - { id: 3, class: _ } +body: | + bb.1.entry: + liveins: $xmm0 + + ; FAST-LABEL: name: test_fptrunc + ; FAST: liveins: $xmm0 + ; FAST: [[COPY:%[0-9]+]]:vecr(s128) = COPY $xmm0 + ; FAST: [[TRUNC:%[0-9]+]]:vecr(s64) = G_TRUNC [[COPY]](s128) + ; FAST: [[FPTRUNC:%[0-9]+]]:vecr(s32) = G_FPTRUNC [[TRUNC]](s64) + ; FAST: [[ANYEXT:%[0-9]+]]:vecr(s128) = G_ANYEXT [[FPTRUNC]](s32) + ; FAST: $xmm0 = COPY [[ANYEXT]](s128) + ; FAST: RET 0, implicit $xmm0 + ; GREEDY-LABEL: name: test_fptrunc + ; GREEDY: liveins: $xmm0 + ; GREEDY: [[COPY:%[0-9]+]]:vecr(s128) = COPY $xmm0 + ; GREEDY: [[TRUNC:%[0-9]+]]:vecr(s64) = G_TRUNC [[COPY]](s128) + ; GREEDY: [[FPTRUNC:%[0-9]+]]:vecr(s32) = G_FPTRUNC [[TRUNC]](s64) + ; GREEDY: [[ANYEXT:%[0-9]+]]:vecr(s128) = G_ANYEXT [[FPTRUNC]](s32) + ; GREEDY: $xmm0 = COPY [[ANYEXT]](s128) + ; GREEDY: RET 0, implicit $xmm0 + %1:_(s128) = COPY $xmm0 + %0:_(s64) = G_TRUNC %1(s128) + %2:_(s32) = G_FPTRUNC %0(s64) + %3:_(s128) = G_ANYEXT %2(s32) + $xmm0 = COPY %3(s128) + RET 0, implicit $xmm0 + +... +--- name: test_fconstant # ALL-LABEL: name: test_fconstant legalized: true diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-fptrunc-scalar.mir b/llvm/test/CodeGen/X86/GlobalISel/select-fptrunc-scalar.mir new file mode 100644 index 0000000..3b25972 --- /dev/null +++ b/llvm/test/CodeGen/X86/GlobalISel/select-fptrunc-scalar.mir @@ -0,0 +1,41 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=x86_64-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL +--- | + + define float @test_fptrunc(double %in) { + %res = fptrunc double %in to float + ret float %res + } + +... +--- +name: test_fptrunc +alignment: 4 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: vecr } + - { id: 1, class: vecr } + - { id: 2, class: vecr } + - { id: 3, class: vecr } +body: | + bb.1 (%ir-block.0): + liveins: $xmm0 + + ; ALL-LABEL: name: test_fptrunc + ; ALL: liveins: $xmm0 + ; ALL: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0 + ; ALL: [[COPY1:%[0-9]+]]:fr64 = COPY [[COPY]] + ; ALL: [[CVTSD2SSrr:%[0-9]+]]:fr32 = CVTSD2SSrr [[COPY1]] + ; ALL: [[COPY2:%[0-9]+]]:vr128 = COPY [[CVTSD2SSrr]] + ; ALL: $xmm0 = COPY [[COPY2]] + ; ALL: RET 0, implicit $xmm0 + %1:vecr(s128) = COPY $xmm0 + %0:vecr(s64) = G_TRUNC %1(s128) + %2:vecr(s32) = G_FPTRUNC %0(s64) + %3:vecr(s128) = G_ANYEXT %2(s32) + $xmm0 = COPY %3(s128) + RET 0, implicit $xmm0 + +... diff --git a/llvm/test/CodeGen/X86/GlobalISel/x86_64-irtranslator.ll b/llvm/test/CodeGen/X86/GlobalISel/x86_64-irtranslator.ll index 907a8fd..6f9d46b 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/x86_64-irtranslator.ll +++ b/llvm/test/CodeGen/X86/GlobalISel/x86_64-irtranslator.ll @@ -185,3 +185,16 @@ define i64 @test_sdiv_i64(i64 %arg1, i64 %arg2) { %res = sdiv i64 %arg1, %arg2 ret i64 %res } +define float @test_fptrunc(double %in) { + ; CHECK-LABEL: name: test_fptrunc + ; CHECK: bb.1 (%ir-block.0): + ; CHECK: liveins: $xmm0 + ; CHECK: [[COPY:%[0-9]+]]:_(s128) = COPY $xmm0 + ; CHECK: [[TRUNC:%[0-9]+]]:_(s64) = G_TRUNC [[COPY]](s128) + ; CHECK: [[FPTRUNC:%[0-9]+]]:_(s32) = G_FPTRUNC [[TRUNC]](s64) + ; CHECK: [[ANYEXT:%[0-9]+]]:_(s128) = G_ANYEXT [[FPTRUNC]](s32) + ; CHECK: $xmm0 = COPY [[ANYEXT]](s128) + ; CHECK: RET 0, implicit $xmm0 + %res = fptrunc double %in to float + ret float %res +}