From: bellard <bellard@c046a42c-6fe2-441c-8c8c-71466251a162>
Date: Mon, 22 May 2006 22:03:52 +0000 (+0000)
Subject: mips cleanup (Thiemo Seufer)
X-Git-Tag: TizenStudio_2.0_p2.3~14285
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=9d05095e5fc0609bfb1f46379791abb664680e4b;p=sdk%2Femulator%2Fqemu.git

mips cleanup (Thiemo Seufer)


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1934 c046a42c-6fe2-441c-8c8c-71466251a162
---

diff --git a/cpu-exec.c b/cpu-exec.c
index 8a585c1..b6df3be 100644
--- a/cpu-exec.c
+++ b/cpu-exec.c
@@ -561,6 +561,8 @@ int cpu_exec(CPUState *env1)
 #elif defined(TARGET_SH4)
 		    /* XXXXX */
 #endif
+                   /* Don't use the cached interupt_request value,
+                      do_interrupt may have updated the EXITTB flag. */
                     if (env->interrupt_request & CPU_INTERRUPT_EXITTB) {
                         env->interrupt_request &= ~CPU_INTERRUPT_EXITTB;
                         /* ensure that no TB jump will be modified as
diff --git a/target-mips/helper.c b/target-mips/helper.c
index 752ee72..d3c64bb 100644
--- a/target-mips/helper.c
+++ b/target-mips/helper.c
@@ -219,7 +219,6 @@ int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
                 exception = EXCP_TLBS;
             else
                 exception = EXCP_TLBL;
-            error_code = 0;
             break;
         case -4:
             /* TLB match but 'D' bit is cleared */
@@ -350,7 +349,6 @@ void do_interrupt (CPUState *env)
         cause = 4;
         goto set_EPC;
     case EXCP_TLBL:
-    case EXCP_TLBF:
         cause = 2;
         if (env->error_code == 1 && !(env->hflags & MIPS_HFLAG_EXL))
             offset = 0x000;