From: daeinki Date: Thu, 21 May 2009 06:18:46 +0000 (+0900) Subject: [S5PC100] Modified functions of init_sequence. X-Git-Tag: s5pc110_universal_support~304^2~1 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=9cf4fc0cbf7c7e2ba90b958568b1c765d2398548;p=kernel%2Fu-boot.git [S5PC100] Modified functions of init_sequence. Signed-off-by: daeinki --- diff --git a/board/samsung/tt/tt.c b/board/samsung/tt/tt.c index fa10b06..ba29235 100644 --- a/board/samsung/tt/tt.c +++ b/board/samsung/tt/tt.c @@ -32,15 +32,6 @@ #include #include -/* ------------------------------------------------------------------------- */ -#define CS8900_Tacs 0x0 /* 0clk address set-up */ -#define CS8900_Tcos 0x4 /* 4clk chip selection set-up */ -#define CS8900_Tacc 0xE /* 14clk access cycle */ -#define CS8900_Tcoh 0x1 /* 1clk chip selection hold */ -#define CS8900_Tah 0x4 /* 4clk address holding time */ -#define CS8900_Tacp 0x6 /* 6clk page mode access cycle */ -#define CS8900_PMC 0x0 /* normal(1data)page mode configuration */ - static inline void delay(unsigned long loops) { __asm__ volatile ("1:\n" "subs %0, %1, #1\n" @@ -48,30 +39,10 @@ static inline void delay(unsigned long loops) : "=r" (loops) : "0" (loops)); } -/* - * Miscellaneous platform dependent initialisations - */ - -static void cs8900_pre_init(void) -{ - SROM_BW_REG &= ~(0xf << 4); - SROM_BW_REG |= (1 << 7) | (1 << 6) | (1 << 4); - SROM_BC1_REG = ((CS8900_Tacs << 28) + (CS8900_Tcos << 24) + - (CS8900_Tacc << 16) + (CS8900_Tcoh << 12) + - (CS8900_Tah << 8) + (CS8900_Tacp << 4) + CS8900_PMC); -} - int board_init(void) { DECLARE_GLOBAL_DATA_PTR; - cs8900_pre_init(); - - /* NOR-flash in SROM0 */ - - /* Enable WAIT */ - SROM_BW_REG |= 4 | 8 | 1; - //gd->bd->bi_arch_number = MACH_TYPE; gd->bd->bi_arch_number = 200; gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; @@ -92,7 +63,7 @@ int dram_init(void) #ifdef CONFIG_DISPLAY_BOARDINFO int checkboard(void) { - printf("Board: SMDK6400\n"); + printf("Board: TT(S5PC100)\n"); return 0; } #endif diff --git a/cpu/arm_cortexa8/s5pc100/interrupts.c b/cpu/arm_cortexa8/s5pc100/interrupts.c index b00e89d..52d08c1 100644 --- a/cpu/arm_cortexa8/s5pc100/interrupts.c +++ b/cpu/arm_cortexa8/s5pc100/interrupts.c @@ -70,34 +70,32 @@ int interrupt_init(void) { s3c64xx_timers *const timers = s3c64xx_get_base_timers(); - /* use PWM Timer 4 because it has no output */ - /* - * We use the following scheme for the timer: - * Prescaler is hard fixed at 167, divider at 1/4. - * This gives at PCLK frequency 66MHz approx. 10us ticks - * The timer is set to wrap after 100s, at 66MHz this obviously - * happens after 10,000,000 ticks. A long variable can thus - * keep values up to 40,000s, i.e., 11 hours. This should be - * enough for most uses:-) Possible optimizations: select a - * binary-friendly frequency, e.g., 1ms / 128. Also calculate - * the prescaler automatically for other PCLK frequencies. - */ - timers->TCFG0 = PRESCALER << 8; + /* use PWM Timer 4 because it has no ouput */ + /* prescaler for timer 4 is 16 */ + timers->TCFG0 = TCFG0_PRE1(16-1); if (timer_load_val == 0) { - timer_load_val = get_PCLK() / PRESCALER * (100 / 4); /* 100s */ - timers->TCFG1 = (timers->TCFG1 & ~0xf0000) | 0x20000; + /* + * for 10 ms clock period @ PCLK with 4 bit divider = 1/2 + * (default) and prescaler = 16. Should be 20859 + * @66.75MHz + */ + timers->TCFG1 = TCFG1_MUX4(2-1); + timer_load_val = get_PCLK() / (2 * 16 * 100); } /* load value for 10 ms timeout */ lastdec = timers->TCNTB4 = timer_load_val; + /* auto load, manual update of Timer 4 */ - timers->TCON = (timers->TCON & ~0x00700000) | TCON_4_AUTO | - TCON_4_UPDATE; + timers->TCON = (timers->TCON & ~0x00700000) | TCON_4_AUTO | TCON_4_UPDATE; - /* auto load, start Timer 4 */ + /* auto load, start timer 4 */ timers->TCON = (timers->TCON & ~0x00700000) | TCON_4_AUTO | COUNT_4_ON; timestamp = 0; + /* usb OTG */ + __REG(ELFIN_VIC1_BASE_ADDR + 0x10) |= 1<<24; + return 0; } diff --git a/cpu/arm_cortexa8/s5pc100/speed.c b/cpu/arm_cortexa8/s5pc100/speed.c index 43850d6..45e05cd 100644 --- a/cpu/arm_cortexa8/s5pc100/speed.c +++ b/cpu/arm_cortexa8/s5pc100/speed.c @@ -94,34 +94,31 @@ ulong get_HCLK(void) { ulong fclk; - uint hclkx2_div = ((CLK_DIV0_REG >> 9) & 0x7) + 1; - uint hclk_div = ((CLK_DIV0_REG >> 8) & 0x1) + 1; + uint div, div_apll, div_arm, div_d0_bus; - /* - * Bit 7 exists on s3c6410, and not on s3c6400, it is reserved on - * s3c6400 and is always 0, and it is indeed running in ASYNC mode - */ - if (OTHERS_REG & 0x80) - fclk = get_FCLK(); /* SYNC Mode */ - else - fclk = get_PLLCLK(MPLL); /* ASYNC Mode */ + div = CLK_DIV0_REG; + + div_apll = (div & 0x1) + 1; + div_arm = ((div >> 4) & 0x7) + 1; + div_d0_bus = ((div >> 8) & 0x7) + 1; - return fclk / (hclk_div * hclkx2_div); + fclk = get_FCLK(); + + return fclk / (div_apll * div_arm * div_d0_bus); } /* return PCLK frequency */ ulong get_PCLK(void) { ulong fclk; - uint hclkx2_div = ((CLK_DIV0_REG >> 9) & 0x7) + 1; - uint pre_div = ((CLK_DIV0_REG >> 12) & 0xf) + 1; + uint div = CLK_DIV1_REG; + uint div_d1_bus = ((div >> 12) & 0x7) + 1; + uint div_pclk = ((div >> 16) & 0x7) + 1; - if (OTHERS_REG & 0x80) - fclk = get_FCLK(); /* SYNC Mode */ - else - fclk = get_PLLCLK(MPLL); /* ASYNC Mode */ + /* ASYNC Mode */ + fclk = get_PLLCLK(MPLL); - return fclk / (hclkx2_div * pre_div); + return fclk/(div_d1_bus * div_pclk); } /* return UCLK frequency */ @@ -132,7 +129,7 @@ ulong get_UCLK(void) int print_cpuinfo(void) { - printf("\nCPU: S3C6400@%luMHz\n", get_ARMCLK() / 1000000); + printf("\nCPU: S5PC100@%luMHz\n", get_ARMCLK() / 1000000); printf(" Fclk = %luMHz, Hclk = %luMHz, Pclk = %luMHz ", get_FCLK() / 1000000, get_HCLK() / 1000000, get_PCLK() / 1000000); diff --git a/cpu/arm_cortexa8/start.S b/cpu/arm_cortexa8/start.S index ec4e98e..f00aaf3 100644 --- a/cpu/arm_cortexa8/start.S +++ b/cpu/arm_cortexa8/start.S @@ -194,23 +194,21 @@ cpu_init_crit: /* * Invalidate L1 I/D */ -/* mov r0, #0 @ set up for MCR mcr p15, 0, r0, c8, c7, 0 @ invalidate TLBs mcr p15, 0, r0, c7, c5, 0 @ invalidate icache -*/ /* * disable MMU stuff and caches */ -/* + /* mrc p15, 0, r0, c1, c0, 0 bic r0, r0, #0x00002000 @ clear bits 13 (--V-) bic r0, r0, #0x00000007 @ clear bits 2:0 (-CAM) orr r0, r0, #0x00000002 @ set bit 1 (--A-) Align orr r0, r0, #0x00000800 @ set bit 12 (Z---) BTB mcr p15, 0, r0, c1, c0, 0 -*/ + */ /* * Jump to board specific initialization... * The Mask ROM will have already initialized diff --git a/drivers/serial/s5pc100.c b/drivers/serial/s5pc100.c index 0bc7724..17d138f 100644 --- a/drivers/serial/s5pc100.c +++ b/drivers/serial/s5pc100.c @@ -26,13 +26,13 @@ #include #ifdef CONFIG_SERIAL0 -#define UART_NR S3C64XX_UART0 +#define UART_NR S5PC1XX_UART0 #elif defined(CONFIG_SERIAL1) -#define UART_NR S3C64XX_UART1 +#define UART_NR S5PC1XX_UART1 #elif defined(CONFIG_SERIAL2) -#define UART_NR S3C64XX_UART2 +#define UART_NR S5PC1XX_UART2 #elif defined(CONFIG_SERIAL3) -#define UART_NR S3C64XX_UART3 +#define UART_NR S5PC1XX_UART3 #else #error "Bad: you didn't configure serial ..." #endif @@ -40,7 +40,7 @@ #define barrier() asm volatile("" ::: "memory") /* - * The coefficient, used to calculate the baudrate on S3C6400 UARTs is + * The coefficient, used to calculate the baudrate on S5PC1XX UARTs is * calculated as * C = UBRDIV * 16 + number_of_set_bits_in_UDIVSLOT * however, section 31.6.11 of the datasheet doesn't recomment using 1 for 1, @@ -68,7 +68,7 @@ static const int udivslot[] = { void serial_setbrg(void) { DECLARE_GLOBAL_DATA_PTR; - s3c64xx_uart *const uart = s3c64xx_get_base_uart(UART_NR); + s5pc1xx_uart *const uart = s5pc1xx_get_base_uart(UART_NR); u32 pclk = get_PCLK(); u32 baudrate = gd->baudrate; int i; @@ -88,7 +88,7 @@ void serial_setbrg(void) */ int serial_init(void) { - s3c64xx_uart *const uart = s3c64xx_get_base_uart(UART_NR); + s5pc1xx_uart *const uart = s5pc1xx_get_base_uart(UART_NR); /* reset and enable FIFOs, set triggers to the maximum */ uart->UFCON = 0; @@ -110,7 +110,7 @@ int serial_init(void) */ int serial_getc(void) { - s3c64xx_uart *const uart = s3c64xx_get_base_uart(UART_NR); + s5pc1xx_uart *const uart = s5pc1xx_get_base_uart(UART_NR); /* wait for character to arrive */ while (!(uart->UTRSTAT & 0x1)); @@ -137,7 +137,7 @@ void enable_putc(void) */ void serial_putc(const char c) { - s3c64xx_uart *const uart = s3c64xx_get_base_uart(UART_NR); + s5pc1xx_uart *const uart = s5pc1xx_get_base_uart(UART_NR); #ifdef CONFIG_MODEM_SUPPORT if (be_quiet) @@ -159,7 +159,7 @@ void serial_putc(const char c) */ int serial_tstc(void) { - s3c64xx_uart *const uart = s3c64xx_get_base_uart(UART_NR); + s5pc1xx_uart *const uart = s5pc1xx_get_base_uart(UART_NR); return uart->UTRSTAT & 0x1; } diff --git a/include/configs/s5pc100_tt.h b/include/configs/s5pc100_tt.h index 9ad8d46..21d88a5 100644 --- a/include/configs/s5pc100_tt.h +++ b/include/configs/s5pc100_tt.h @@ -41,6 +41,7 @@ #define CONFIG_SAMSUNG 1 /* in a SAMSUNG core */ #define CONFIG_S5PC100 1 /* which is in a S5PC100 */ #define CONFIG_S5PC100_TT 1 /* working with TT */ +//#define CONFIG_S5PC1XX_I2C #include /* get chip and board defs */ #include @@ -93,6 +94,12 @@ */ #define CONFIG_SERIAL2 1 /* we use SERIAL 2 on S5PC100 */ +#ifdef CONFIG_S5PC1XX_I2C /* use H/W I2C for PMIC & USB switch */ +#define CONFIG_HARD_I2C 1 +#define CFG_I2C_SPEED 50000 +#define CFG_I2C_SLAVE 0xFE +#endif + #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ #ifdef CONFIG_SYS_HUSH_PARSER #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " @@ -184,8 +191,8 @@ /* SMDK6400 has 2 banks of DRAM, but we use only one in U-Boot */ #define CONFIG_NR_DRAM_BANKS 1 -#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE /* SDRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB in Bank #1 */ +#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE /* SDRAM Bank #1 */ +#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB in Bank #1 */ #define CONFIG_SYS_FLASH_BASE 0x10000000 #define CONFIG_SYS_MONITOR_BASE 0x00000000 diff --git a/include/s5pc100.h b/include/s5pc100.h index 272341a..09ee480 100644 --- a/include/s5pc100.h +++ b/include/s5pc100.h @@ -35,13 +35,13 @@ #define APLL_LOCK_OFFSET 0x00 #define MPLL_LOCK_OFFSET 0x04 #define EPLL_LOCK_OFFSET 0x08 -#define APLL_CON_OFFSET 0x0C -#define MPLL_CON_OFFSET 0x10 -#define EPLL_CON0_OFFSET 0x14 +#define APLL_CON_OFFSET 0x100 +#define MPLL_CON_OFFSET 0x104 +#define EPLL_CON0_OFFSET 0x108 #define EPLL_CON1_OFFSET 0x18 #define CLK_SRC_OFFSET 0x1C -#define CLK_DIV0_OFFSET 0x20 -#define CLK_DIV1_OFFSET 0x24 +#define CLK_DIV0_OFFSET 0x300 +#define CLK_DIV1_OFFSET 0x304 #define CLK_DIV2_OFFSET 0x28 #define CLK_OUT_OFFSET 0x2C #define HCLK_GATE_OFFSET 0x30 @@ -837,6 +837,7 @@ #define TCFG0_DZONE(x) FInsrt((x), fTCFG0_DZONE) #define TCFG0_PRE1(x) FInsrt((x), fTCFG0_PRE1) #define TCFG0_PRE0(x) FInsrt((x), fTCFG0_PRE0) +#define TCFG1_MUX4(x) FInsrt((x), fTCFG1_MUX4) #define TCON_4_AUTO (1 << 22) /* auto reload on/off for Timer 4 */ #define TCON_4_UPDATE (1 << 21) /* manual Update TCNTB4 */ #define TCON_4_ONOFF (1 << 20) /* 0: Stop, 1: start Timer 4 */ @@ -971,22 +972,22 @@ #define DMC_DDR_USER_CONFIG 1 #ifndef __ASSEMBLY__ -enum s3c64xx_uarts_nr { - S3C64XX_UART0, - S3C64XX_UART1, - S3C64XX_UART2, - S3C64XX_UART3, +enum s5pc1xx_uarts_nr { + S5PC1XX_UART0, + S5PC1XX_UART1, + S5PC1XX_UART2, + S5PC1XX_UART3, }; -#include "s3c64x0.h" +#include "s5pc1x0.h" -static inline s3c64xx_uart *s3c64xx_get_base_uart(enum s3c64xx_uarts_nr nr) +static inline s5pc1xx_uart *s5pc1xx_get_base_uart(enum s5pc1xx_uarts_nr nr) { - return (s3c64xx_uart *)(ELFIN_UART_BASE + (nr * 0x400)); + return (s5pc1xx_uart *)(ELFIN_UART_BASE + (nr * 0x400)); } #endif -#endif /*__S3C6400_H__*/ +#endif diff --git a/include/s5pc1x0.h b/include/s5pc1x0.h index 686d6d5..435ac59 100644 --- a/include/s5pc1x0.h +++ b/include/s5pc1x0.h @@ -31,8 +31,8 @@ * common stuff for SAMSUNG S3C64XX SoC ************************************************/ -#ifndef __S3C64XX_H__ -#define __S3C64XX_H__ +#ifndef __S5PC1XX_H__ +#define __S5PC1XX_H__ #if defined(CONFIG_SYNC_MODE) && defined(CONFIG_S3C6400) #error CONFIG_SYNC_MODE unavailable on S3C6400, please, fix your configuration! @@ -62,7 +62,14 @@ typedef struct { volatile u8 res2[3]; #endif volatile u32 UBRDIV; -} s3c64xx_uart; +#ifdef __BIG_ENDIAN + volatile u8 res3[2]; + volatile u16 UDIVSLOT; +#else + volatile u16 UDIVSLOT; + volatile u8 res3[2]; +#endif +} s5pc1xx_uart; /* PWM TIMER (see manual chapter 10) */ typedef struct { @@ -80,4 +87,4 @@ typedef struct { volatile u32 TCNTO4; } s3c64xx_timers; -#endif /*__S3C64XX_H__*/ +#endif diff --git a/include/s5pc1xx.h b/include/s5pc1xx.h index d614f58..631f6b2 100644 --- a/include/s5pc1xx.h +++ b/include/s5pc1xx.h @@ -12,22 +12,24 @@ #include #define S5P_ADDR_BASE (0xe0000000) - #define S5P_ADDR(x) (S5P_ADDR_BASE + (x)) #define S5P_PA_ID S5P_ADDR(0x00000000) /* ID Base */ #define S5P_PA_CLK S5P_ADDR(0x00100000) /* Clock Base */ #define S5P_PA_PWR S5P_ADDR(0x00108000) /* Power Base */ #define S5P_PA_CLK_OTHERS S5P_ADDR(0x00200000) /* Clock Others Base */ -#define S5P_PA_GPIO S5P_ADDR(0x00300000) /* GPIO Base */ -#define S5P_PA_VIC0 S5P_ADDR(0x04000000) /* Interrupt Controller 0 */ -#define S5P_PA_VIC1 S5P_ADDR(0x04100000) /* Interrupt Controller 1 */ -#define S5P_PA_VIC2 S5P_ADDR(0x04200000) /* Interrupt Controller 3 */ -#define S5P_PA_SROM S5P_ADDR(0x07000000) /* SROM */ -#define S5P_PA_ONENAND S5P_ADDR(0x07100000) /* ONENAND */ -#define S5P_PA_NAND S5P_ADDR(0x07200000) /* NAND */ -#define S5P_PA_PWMTIMER S5P_ADDR(0x0a000000) /* PWM Timer */ -#define S5P_PA_WATCHDOG S5P_ADDR(0x0a200000) /* Watchdog Timer */ +#define S5P_PA_GPIO S5P_ADDR(0x00300000) /* GPIO Base */ +#define S5P_PA_VIC0 S5P_ADDR(0x04000000) /* Vector Interrupt Controller 0 */ +#define S5P_PA_VIC1 S5P_ADDR(0x04100000) /* Vector Interrupt Controller 1 */ +#define S5P_PA_VIC2 S5P_ADDR(0x04200000) /* Vector Interrupt Controller 2 */ +#define S5P_PA_TZIC0 S5P_ADDR(0x05000000) /* TrustZone Interrupt Controller 0 */ +#define S5P_PA_TZIC1 S5P_ADDR(0x05100000) /* TrustZone Interrupt Controller 1 */ +#define S5P_PA_TZIC2 S5P_ADDR(0x05200000) /* TrustZone Interrupt Controller 2 */ +#define S5P_PA_DMC S5P_ADDR(0x06000000) /* Dram Memory Controller */ +#define S5P_PA_SROMC S5P_ADDR(0x07000000) /* SROM Controller */ +#define S5P_PA_ONENANDC S5P_ADDR(0x07100000) /* OneNand Controller */ +#define S5P_PA_PWMTIMER S5P_ADDR(0x0a000000) /* PWM Timer */ +#define S5P_PA_WATCHDOG S5P_ADDR(0x0a200000) /* Watchdog Timer */ #define S5P_PA_SYSTEM S5P_ADDR(0x0a100000) /* System Timer */ #define S5P_PA_RTC S5P_ADDR(0x0a300000) /* RTC */ #define S5P_PA_UART S5P_ADDR(0x0c000000) /* Uart Base */ @@ -719,7 +721,7 @@ /* - * Interrupt + * Vector Interrupt Controller * : VIC0, VIC1, VIC2 */ #define S5P_PA_VIC0 S5P_ADDR(0x04000000) /* Interrupt Controller 0 */ @@ -732,29 +734,30 @@ #define S5P_VIC0_VECT_PRIO_BASE(x) (S5P_PA_VIC0 + 0x200 + (x)) #define S5P_VIC0_ADDRESS_BASE(x) (S5P_PA_VIC0 + 0xf00 + (x)) -#define IRQSTATUS_OFFSET 0x0 /* IRQ Status Register */ -#define FIQSTATUS_OFFSET 0x4 /* FIQ Status Register */ -#define RAWINTR_OFFSET 0x8 /* Raw Interrupt Status Register */ -#define INTSELECT_OFFSET 0xc /* Interrupt Select Register */ -#define INTENABLE_OFFSET 0x10 /* Interrupt Enable Register */ -#define INTENCLEAR_OFFSET 0x14 /* Interrupt Enable Clear Register */ -#define SOFTINT_OFFSET 0x18 /* Software Interrupt Register */ -#define SOFTINTCLEAR_OFFSET 0x1c /* Software Interrupt Clear Register */ -#define PROTECTION_OFFSET 0x20 /* Protection Enable Register */ -#define SWPRIORITYMASK_OFFSET 0x24 /* Software Priority Mask Register */ -#define PRIORITYDAISY_OFFSET 0x28 /* Vector Priority Register for Daisy Chain */ - -#define S5P_VIC0IRQSTATUS S5P_VIC0_BASE(IRQSTATUS_OFFSET) -#define S5P_VIC0FIQSTATUS S5P_VIC0_BASE(FIQSTATUS_OFFSET) -#define S5P_VIC0RAWINTR S5P_VIC0_BASE(RAWINTR_OFFSET) -#define S5P_VIC0INTSELECT S5P_VIC0_BASE(INTSELECT_OFFSET) -#define S5P_VIC0INTENABLE S5P_VIC0_BASE(INTENABLE_OFFSET) -#define S5P_VIC0INTENCLEAR S5P_VIC0_BASE(INTENCLEAR_OFFSET) -#define S5P_VIC0SOFTINT S5P_VIC0_BASE(SOFTINT_OFFSET) -#define S5P_VIC0SOFTINTCLEAR S5P_VIC0_BASE(SOFTINTCLEAR_OFFSET) -#define S5P_VIC0PROTECTION S5P_VIC0_BASE(PROTECTION_OFFSET) -#define S5P_VIC0SWPRIORITYMASK S5P_VIC0_BASE(SWPRIORITYMASK_OFFSET) -#define S5P_VIC0PRIORITYDAISY S5P_VIC0_BASE(PRIORITYDAISY_OFFSET) +/* Vector Interrupt Offset */ +#define VIC_IRQSTATUS_OFFSET 0x0 /* IRQ Status Register */ +#define VIC_FIQSTATUS_OFFSET 0x4 /* FIQ Status Register */ +#define VIC_RAWINTR_OFFSET 0x8 /* Raw Interrupt Status Register */ +#define VIC_INTSELECT_OFFSET 0xc /* Interrupt Select Register */ +#define VIC_INTENABLE_OFFSET 0x10 /* Interrupt Enable Register */ +#define VIC_INTENCLEAR_OFFSET 0x14 /* Interrupt Enable Clear Register */ +#define VIC_SOFTINT_OFFSET 0x18 /* Software Interrupt Register */ +#define VIC_SOFTINTCLEAR_OFFSET 0x1c /* Software Interrupt Clear Register */ +#define VIC_PROTECTION_OFFSET 0x20 /* Protection Enable Register */ +#define VIC_SWPRIORITYMASK_OFFSET 0x24 /* Software Priority Mask Register */ +#define VIC_PRIORITYDAISY_OFFSET 0x28 /* Vector Priority Register for Daisy Chain */ + +#define S5P_VIC0IRQSTATUS S5P_VIC0_BASE(VIC_IRQSTATUS_OFFSET) +#define S5P_VIC0FIQSTATUS S5P_VIC0_BASE(VIC_FIQSTATUS_OFFSET) +#define S5P_VIC0RAWINTR S5P_VIC0_BASE(VIC_RAWINTR_OFFSET) +#define S5P_VIC0INTSELECT S5P_VIC0_BASE(VIC_INTSELECT_OFFSET) +#define S5P_VIC0INTENABLE S5P_VIC0_BASE(VIC_INTENABLE_OFFSET) +#define S5P_VIC0INTENCLEAR S5P_VIC0_BASE(VIC_INTENCLEAR_OFFSET) +#define S5P_VIC0SOFTINT S5P_VIC0_BASE(VIC_SOFTINT_OFFSET) +#define S5P_VIC0SOFTINTCLEAR S5P_VIC0_BASE(VIC_SOFTINTCLEAR_OFFSET) +#define S5P_VIC0PROTECTION S5P_VIC0_BASE(VIC_PROTECTION_OFFSET) +#define S5P_VIC0SWPRIORITYMASK S5P_VIC0_BASE(VIC_SWPRIORITYMASK_OFFSET) +#define S5P_VIC0PRIORITYDAISY S5P_VIC0_BASE(VIC_PRIORITYDAISY_OFFSET) #define S5P_VIC0VECTADDR0 S5P_VIC0_VECT_ADDR_BASE(0x00) #define S5P_VIC0VECTADDR1 S5P_VIC0_VECT_ADDR_BASE(0x04) @@ -839,29 +842,29 @@ #define S5P_VIC1_VECT_PRIO_BASE(x) (S5P_PA_VIC1 + 0x200 + (x)) #define S5P_VIC1_ADDRESS_BASE(x) (S5P_PA_VIC1 + 0xf00 + (x)) -#define IRQSTATUS_OFFSET 0x0 /* IRQ Status Register */ -#define FIQSTATUS_OFFSET 0x4 /* FIQ Status Register */ -#define RAWINTR_OFFSET 0x8 /* Raw Interrupt Status Register */ -#define INTSELECT_OFFSET 0xc /* Interrupt Select Register */ -#define INTENABLE_OFFSET 0x10 /* Interrupt Enable Register */ -#define INTENCLEAR_OFFSET 0x14 /* Interrupt Enable Clear Register */ -#define SOFTINT_OFFSET 0x18 /* Software Interrupt Register */ -#define SOFTINTCLEAR_OFFSET 0x1c /* Software Interrupt Clear Register */ -#define PROTECTION_OFFSET 0x20 /* Protection Enable Register */ -#define SWPRIORITYMASK_OFFSET 0x24 /* Software Priority Mask Register */ -#define PRIORITYDAISY_OFFSET 0x28 /* Vector Priority Register for Daisy Chain */ - -#define S5P_VIC1IRQSTATUS S5P_VIC1_BASE(IRQSTATUS_OFFSET) -#define S5P_VIC1FIQSTATUS S5P_VIC1_BASE(FIQSTATUS_OFFSET) -#define S5P_VIC1RAWINTR S5P_VIC1_BASE(RAWINTR_OFFSET) -#define S5P_VIC1INTSELECT S5P_VIC1_BASE(INTSELECT_OFFSET) -#define S5P_VIC1INTENABLE S5P_VIC1_BASE(INTENABLE_OFFSET) -#define S5P_VIC1INTENCLEAR S5P_VIC1_BASE(INTENCLEAR_OFFSET) -#define S5P_VIC1SOFTINT S5P_VIC1_BASE(SOFTINT_OFFSET) -#define S5P_VIC1SOFTINTCLEAR S5P_VIC1_BASE(SOFTINTCLEAR_OFFSET) -#define S5P_VIC1PROTECTION S5P_VIC1_BASE(PROTECTION_OFFSET) -#define S5P_VIC1SWPRIORITYMASK S5P_VIC1_BASE(SWPRIORITYMASK_OFFSET) -#define S5P_VIC1PRIORITYDAISY S5P_VIC1_BASE(PRIORITYDAISY_OFFSET) +//#define VIC_IRQSTATUS_OFFSET 0x0 /* IRQ Status Register */ +//#define FIQSTATUS_OFFSET 0x4 /* FIQ Status Register */ +//#define RAWINTR_OFFSET 0x8 /* Raw Interrupt Status Register */ +//#define VIC_INTSELECT_OFFSET 0xc /* Interrupt Select Register */ +//#define INTENABLE_OFFSET 0x10 /* Interrupt Enable Register */ +//#define INTENCLEAR_OFFSET 0x14 /* Interrupt Enable Clear Register */ +//#define SOFTINT_OFFSET 0x18 /* Software Interrupt Register */ +//#define SOFTINTCLEAR_OFFSET 0x1c /* Software Interrupt Clear Register */ +//#define PROTECTION_OFFSET 0x20 /* Protection Enable Register */ +//#define SWPRIORITYMASK_OFFSET 0x24 /* Software Priority Mask Register */ +//#define PRIORITYDAISY_OFFSET 0x28 /* Vector Priority Register for Daisy Chain */ + +#define S5P_VIC1IRQSTATUS S5P_VIC1_BASE(VIC_IRQSTATUS_OFFSET) +#define S5P_VIC1FIQSTATUS S5P_VIC1_BASE(VIC_FIQSTATUS_OFFSET) +#define S5P_VIC1RAWINTR S5P_VIC1_BASE(VIC_RAWINTR_OFFSET) +#define S5P_VIC1INTSELECT S5P_VIC1_BASE(VIC_INTSELECT_OFFSET) +#define S5P_VIC1INTENABLE S5P_VIC1_BASE(VIC_INTENABLE_OFFSET) +#define S5P_VIC1INTENCLEAR S5P_VIC1_BASE(VIC_INTENCLEAR_OFFSET) +#define S5P_VIC1SOFTINT S5P_VIC1_BASE(VIC_SOFTINT_OFFSET) +#define S5P_VIC1SOFTINTCLEAR S5P_VIC1_BASE(VIC_SOFTINTCLEAR_OFFSET) +#define S5P_VIC1PROTECTION S5P_VIC1_BASE(VIC_PROTECTION_OFFSET) +#define S5P_VIC1SWPRIORITYMASK S5P_VIC1_BASE(VIC_SWPRIORITYMASK_OFFSET) +#define S5P_VIC1PRIORITYDAISY S5P_VIC1_BASE(VIC_PRIORITYDAISY_OFFSET) #define S5P_VIC1VECTADDR0 S5P_VIC1_VECT_ADDR_BASE(0x00) #define S5P_VIC1VECTADDR1 S5P_VIC1_VECT_ADDR_BASE(0x04) @@ -946,29 +949,29 @@ #define S5P_VIC2_VECT_PRIO_BASE(x) (S5P_PA_VIC2 + 0x200 + (x)) #define S5P_VIC2_ADDRESS_BASE(x) (S5P_PA_VIC2 + 0xf00 + (x)) -#define IRQSTATUS_OFFSET 0x0 /* IRQ Status Register */ -#define FIQSTATUS_OFFSET 0x4 /* FIQ Status Register */ -#define RAWINTR_OFFSET 0x8 /* Raw Interrupt Status Register */ -#define INTSELECT_OFFSET 0xc /* Interrupt Select Register */ -#define INTENABLE_OFFSET 0x10 /* Interrupt Enable Register */ -#define INTENCLEAR_OFFSET 0x14 /* Interrupt Enable Clear Register */ -#define SOFTINT_OFFSET 0x18 /* Software Interrupt Register */ -#define SOFTINTCLEAR_OFFSET 0x1c /* Software Interrupt Clear Register */ -#define PROTECTION_OFFSET 0x20 /* Protection Enable Register */ -#define SWPRIORITYMASK_OFFSET 0x24 /* Software Priority Mask Register */ -#define PRIORITYDAISY_OFFSET 0x28 /* Vector Priority Register for Daisy Chain */ - -#define S5P_VIC2IRQSTATUS S5P_VIC2_BASE(IRQSTATUS_OFFSET) -#define S5P_VIC2FIQSTATUS S5P_VIC2_BASE(FIQSTATUS_OFFSET) -#define S5P_VIC2RAWINTR S5P_VIC2_BASE(RAWINTR_OFFSET) -#define S5P_VIC2INTSELECT S5P_VIC2_BASE(INTSELECT_OFFSET) -#define S5P_VIC2INTENABLE S5P_VIC2_BASE(INTENABLE_OFFSET) -#define S5P_VIC2INTENCLEAR S5P_VIC2_BASE(INTENCLEAR_OFFSET) -#define S5P_VIC2SOFTINT S5P_VIC2_BASE(SOFTINT_OFFSET) -#define S5P_VIC2SOFTINTCLEAR S5P_VIC2_BASE(SOFTINTCLEAR_OFFSET) -#define S5P_VIC2PROTECTION S5P_VIC2_BASE(PROTECTION_OFFSET) -#define S5P_VIC2SWPRIORITYMASK S5P_VIC2_BASE(SWPRIORITYMASK_OFFSET) -#define S5P_VIC2PRIORITYDAISY S5P_VIC2_BASE(PRIORITYDAISY_OFFSET) +//#define VIC_IRQSTATUS_OFFSET 0x0 /* IRQ Status Register */ +//#define VIC_FIQSTATUS_OFFSET 0x4 /* FIQ Status Register */ +//#define VIC_RAWINTR_OFFSET 0x8 /* Raw Interrupt Status Register */ +//#define VIC_INTSELECT_OFFSET 0xc /* Interrupt Select Register */ +//#define VIC_INTENABLE_OFFSET 0x10 /* Interrupt Enable Register */ +//#define INTENCLEAR_OFFSET 0x14 /* Interrupt Enable Clear Register */ +//#define SOFTINT_OFFSET 0x18 /* Software Interrupt Register */ +//#define SOFTINTCLEAR_OFFSET 0x1c /* Software Interrupt Clear Register */ +//#define PROTECTION_OFFSET 0x20 /* Protection Enable Register */ +//#define SWPRIORITYMASK_OFFSET 0x24 /* Software Priority Mask Register */ +//#define PRIORITYDAISY_OFFSET 0x28 /* Vector Priority Register for Daisy Chain */ + +#define S5P_VIC2IRQSTATUS S5P_VIC2_BASE(VIC_IRQSTATUS_OFFSET) +#define S5P_VIC2FIQSTATUS S5P_VIC2_BASE(VIC_FIQSTATUS_OFFSET) +#define S5P_VIC2RAWINTR S5P_VIC2_BASE(VIC_RAWINTR_OFFSET) +#define S5P_VIC2INTSELECT S5P_VIC2_BASE(VIC_INTSELECT_OFFSET) +#define S5P_VIC2INTENABLE S5P_VIC2_BASE(VIC_INTENABLE_OFFSET) +#define S5P_VIC2INTENCLEAR S5P_VIC2_BASE(VIC_INTENCLEAR_OFFSET) +#define S5P_VIC2SOFTINT S5P_VIC2_BASE(VIC_SOFTINT_OFFSET) +#define S5P_VIC2SOFTINTCLEAR S5P_VIC2_BASE(VIC_SOFTINTCLEAR_OFFSET) +#define S5P_VIC2PROTECTION S5P_VIC2_BASE(VIC_PROTECTION_OFFSET) +#define S5P_VIC2SWPRIORITYMASK S5P_VIC2_BASE(VIC_SWPRIORITYMASK_OFFSET) +#define S5P_VIC2PRIORITYDAISY S5P_VIC2_BASE(VIC_PRIORITYDAISY_OFFSET) #define S5P_VIC2VECTADDR0 S5P_VIC2_VECT_ADDR_BASE(0x00) #define S5P_VIC2VECTADDR1 S5P_VIC2_VECT_ADDR_BASE(0x04) @@ -1049,17 +1052,429 @@ +/* + * TrustZone Interrupt Controller + * : TZI0, TZI1, TZI2 + */ +#define S5P_TZIC0_BASE(x) (S5P_PA_TZIC0 + (x)) +#define S5P_TZIC1_BASE(x) (S5P_PA_TZIC1 + (x)) +#define S5P_TZIC2_BASE(x) (S5P_PA_TZIC2 + (x)) + +#define FIQSTATUS_OFFSET (0x00) /* FIQ Status Regieter */ +#define RAWINTR_OFFSET (0x04) /* Raw Interrupt Status Register */ +#define INTSELECT_OFFSET (0x08) /* Interrupt Select Register */ +#define FIQENABLE_OFFSET (0x0c) /* FIQ Enable Register */ +#define FIQENCLEAR_OFFSET (0x10) /* FIQ Enable Clear Register */ +#define FIQBYPASS_OFFSET (0x14) /* FIQ Bypass Register */ +#define FIQPROTECTION_OFFSET (0x18) /* Protection Register */ +#define FIQLOCK_OFFSET (0x1c) /* Lock Enable Register */ +#define FIQLOCKSTATUS_OFFSET (0x20) /* Lock Status Register */ +#define PERIPHID0_OFFSET (0xfe0) /* Peripheral Identification Register */ +#define PCELLID0_OFFSET (0xff0) /* PrimeCell Identification Register */ + +/* TZI0 */ +#define S5P_TZIC0FIQSTATUS S5P_TZIC0_BASE(FIQSTATUS_OFFSET) +#define S5P_TZIC0RAWINTR S5P_TZIC0_BASE(RAQINTR_OFFSET) +#define S5P_TZIC0INTSELECT S5P_TZIC0_BASE(INTSELECT_OFFSET) +#define S5P_TZIC0FIQENABLE S5P_TZIC0_BASE(FIQENABLE_OFFSET) +#define S5P_TZIC0FIQENCLEAR S5P_TZIC0_BASE(FIQENCLEAR_OFFSET) +#define S5P_TZIC0FIQBYPASS S5P_TZIC0_BASE(FIQBYPASS_OFFSET) +#define S5P_TZIC0FIQPROTECTION S5P_TZIC0_BASE(FIQPROTECTION_OFFSET) +#define S5P_TZIC0FIQLOCK S5P_TZIC0_BASE(FIQLOCKSTATUS_OFFSET) +#define S5P_TZIC0FIQLOCKSTATUS S5P_TZIC0_BASE(PCELLID0_OFFSET) + +#define S5P_TZIC0PERIPHID0 S5P_TZIC0_BASE(PERIPHID0_OFFSET + 0x0) +#define S5P_TZIC0PERIPHID1 S5P_TZIC0_BASE(PERIPHID0_OFFSET + 0x4) +#define S5P_TZIC0PERIPHID2 S5P_TZIC0_BASE(PERIPHID0_OFFSET + 0x8) +#define S5P_TZIC0PERIPHID3 S5P_TZIC0_BASE(PERIPHID0_OFFSET + 0xc) + +#define S5P_TZIC0PCELLID0 S5P_TZIC0_BASE(PCELLID0_OFFSET + 0x0) +#define S5P_TZIC0PCELLID1 S5P_TZIC0_BASE(PCELLID1_OFFSET + 0x0) +#define S5P_TZIC0PCELLID2 S5P_TZIC0_BASE(PCELLID2_OFFSET + 0x0) +#define S5P_TZIC0PCELLID3 S5P_TZIC0_BASE(PCELLID3_OFFSET + 0x0) + +/* TZI1 */ +#define S5P_TZIC1FIQSTATUS S5P_TZIC1_BASE(FIQSTATUS_OFFSET) +#define S5P_TZIC1RAWINTR S5P_TZIC1_BASE(RAQINTR_OFFSET) +#define S5P_TZIC1INTSELECT S5P_TZIC1_BASE(INTSELECT_OFFSET) +#define S5P_TZIC1FIQENABLE S5P_TZIC1_BASE(FIQENABLE_OFFSET) +#define S5P_TZIC1FIQENCLEAR S5P_TZIC1_BASE(FIQENCLEAR_OFFSET) +#define S5P_TZIC1FIQBYPASS S5P_TZIC1_BASE(FIQBYPASS_OFFSET) +#define S5P_TZIC1FIQPROTECTION S5P_TZIC1_BASE(FIQPROTECTION_OFFSET) +#define S5P_TZIC1FIQLOCK S5P_TZIC1_BASE(FIQLOCKSTATUS_OFFSET) +#define S5P_TZIC1FIQLOCKSTATUS S5P_TZIC1_BASE(PCELLID0_OFFSET) + +#define S5P_TZIC1PERIPHID0 S5P_TZIC1_BASE(PERIPHID0_OFFSET + 0x0) +#define S5P_TZIC1PERIPHID1 S5P_TZIC1_BASE(PERIPHID0_OFFSET + 0x4) +#define S5P_TZIC1PERIPHID2 S5P_TZIC1_BASE(PERIPHID0_OFFSET + 0x8) +#define S5P_TZIC1PERIPHID3 S5P_TZIC1_BASE(PERIPHID0_OFFSET + 0xc) + +#define S5P_TZIC1PCELLID0 S5P_TZIC1_BASE(PCELLID0_OFFSET + 0x0) +#define S5P_TZIC1PCELLID1 S5P_TZIC1_BASE(PCELLID1_OFFSET + 0x0) +#define S5P_TZIC1PCELLID2 S5P_TZIC1_BASE(PCELLID2_OFFSET + 0x0) +#define S5P_TZIC1PCELLID3 S5P_TZIC1_BASE(PCELLID3_OFFSET + 0x0) + +/* TZI2 */ +#define S5P_TZIC2FIQSTATUS S5P_TZIC2_BASE(FIQSTATUS_OFFSET) +#define S5P_TZIC2RAWINTR S5P_TZIC2_BASE(RAQINTR_OFFSET) +#define S5P_TZIC2INTSELECT S5P_TZIC2_BASE(INTSELECT_OFFSET) +#define S5P_TZIC2FIQENABLE S5P_TZIC2_BASE(FIQENABLE_OFFSET) +#define S5P_TZIC2FIQENCLEAR S5P_TZIC2_BASE(FIQENCLEAR_OFFSET) +#define S5P_TZIC2FIQBYPASS S5P_TZIC2_BASE(FIQBYPASS_OFFSET) +#define S5P_TZIC2FIQPROTECTION S5P_TZIC2_BASE(FIQPROTECTION_OFFSET) +#define S5P_TZIC2FIQLOCK S5P_TZIC2_BASE(FIQLOCKSTATUS_OFFSET) +#define S5P_TZIC2FIQLOCKSTATUS S5P_TZIC2_BASE(PCELLID0_OFFSET) + +#define S5P_TZIC2PERIPHID0 S5P_TZIC2_BASE(PERIPHID0_OFFSET + 0x0) +#define S5P_TZIC2PERIPHID1 S5P_TZIC2_BASE(PERIPHID0_OFFSET + 0x4) +#define S5P_TZIC2PERIPHID2 S5P_TZIC2_BASE(PERIPHID0_OFFSET + 0x8) +#define S5P_TZIC2PERIPHID3 S5P_TZIC2_BASE(PERIPHID0_OFFSET + 0xc) + +#define S5P_TZIC2PCELLID0 S5P_TZIC2_BASE(PCELLID0_OFFSET + 0x0) +#define S5P_TZIC2PCELLID1 S5P_TZIC2_BASE(PCELLID1_OFFSET + 0x0) +#define S5P_TZIC2PCELLID2 S5P_TZIC2_BASE(PCELLID2_OFFSET + 0x0) +#define S5P_TZIC2PCELLID3 S5P_TZIC2_BASE(PCELLID3_OFFSET + 0x0) + + + /* - * Memory - * : SROM, Onenand, Nand, SDRAM + * Memory : SDRAM, SROM, OneNand */ +/* DRAM Memory Controller */ +#define S5P_DMC_BASE(x) (S5P_PA_DMC + (x)) + +#define CONCONTROL_OFFSET 0x0 /* Controller Control Register */ +#define MEMCONTROL_OFFSET 0x04 /* Memory Control Register */ +#define MEMCONFIG0_OFFSET 0x08 /* Memory Chip0 Configuration Register */ +#define MEMCONFIG1_OFFSET 0x0c /* Memory Chip1 Configuration Register */ +#define DIRECTCMD_OFFSET 0x10 /* Memory Direct Command Register */ +#define PRECHCONFIG_OFFSET 0x14 /* Precharge Policy Configuration Register */ +#define PHYCONTROL0_OFFSET 0x18 /* PHY Control0 Register */ +#define PHYCONTROL1_OFFSET 0x1c /* PHY Control1 Register */ +#define PHYCONTROL2_OFFSET 0x20 /* PHY Control2 Register */ +#define PWRDNCONFIG_OFFSET 0x28 /* Dynamic Power Down Configuration Register */ +#define TIMINGAREF_OFFSET 0x30 /* AC Timing Register for SDRAM Auto Refresh */ +#define TIMINGROW_OFFSET 0x34 /* AC Timing Register for SDRAM Row */ +#define TIMINGDATA_OFFSET 0x38 /* AC Timing Register for SDRAM Data */ +#define TIMINGPOWER_OFFSET 0x3c /* AC Timing Register for Power Mode of SDRAM */ +#define PHYSTATUS0_OFFSET 0x40 /* PHY Status Register 0 */ +#define PHYSTATUS1_OFFSET 0x44 /* PHY Status Register 1 */ +#define CHIP0STATUS_OFFSET 0x48 /* Memory Chip0 Status Register */ +#define CHIP1STATUS_OFFSET 0x4c /* Memory Chip1 Status Register */ +#define AREFSTATUS_OFFSET 0x50 /* Counter status Register for Auto Refresh */ +#define MRSTATUS_OFFSET 0x54 /* Memory Mode Registers Status Register */ +#define PHYTEST0_OFFSET 0x58 /* PHY Test Register 0 */ +#define PHYTEST1_OFFSET 0x5c /* PHY Test Register 1 */ +#define QOSCONTROL0_OFFSET 0x60 /* Quality of Service Control Register 0 */ +#define QOSCONFIG0_OFFSET 0x64 /* Quality of Service Configuration Register 0 */ +#define QOSCONTROL1_OFFSET 0x68 +#define QOSCONFIG1_OFFSET 0x6c +#define QOSCONTROL2_OFFSET 0x70 +#define QOSCONFIG2_OFFSET 0x74 +#define QOSCONTROL3_OFFSET 0x78 +#define QOSCONFIG3_OFFSET 0x7c +#define QOSCONTROL4_OFFSET 0x80 +#define QOSCONFIG4_OFFSET 0x84 +#define QOSCONTROL5_OFFSET 0x88 +#define QOSCONFIG5_OFFSET 0x8c +#define QOSCONTROL6_OFFSET 0x90 +#define QOSCONFIG6_OFFSET 0x94 +#define QOSCONTROL7_OFFSET 0x98 +#define QOSCONFIG7_OFFSET 0x9c + +#define S5P_CONCONTROL S5P_DMC_BASE(CONCONTROL_OFFSET) +#define S5P_MEMCONTROL S5P_DMC_BASE(MEMCONTROL_OFFSET) +#define S5P_MEMCONFIG0 S5P_DMC_BASE(MEMCONFIG0_OFFSET) +#define S5P_MEMCONFIG1 S5P_DMC_BASE(MEMCONFIG1_OFFSET) +#define S5P_DIRECTCMD S5P_DMC_BASE(DIRECTCMD_OFFSET) +#define S5P_PRECHCONFIG S5P_DMC_BASE(PRECHCONFIG_OFFSET) +#define S5P_PHYCONTROL0 S5P_DMC_BASE(PHYCONTROL0_OFFSET) +#define S5P_PHYCONTROL1 S5P_DMC_BASE(PHYCONTROL1_OFFSET) +#define S5P_PHYCONTROL2 S5P_DMC_BASE(PHYCONTROL2_OFFSET) +#define S5P_PWRDNCONFIG S5P_DMC_BASE(PWRDNCONFIG_OFFSET) +#define S5P_TIMINGAREF S5P_DMC_BASE(TIMINGAREF_OFFSET) +#define S5P_TIMINGROW S5P_DMC_BASE(TIMINGROW_OFFSET) +#define S5P_TIMINGDATA S5P_DMC_BASE(TIMINGDATA_OFFSET) +#define S5P_TIMINGPOWER S5P_DMC_BASE(TIMINGPOWER_OFFSET) +#define S5P_PHYSTATUS0 S5P_DMC_BASE(PHYSTATUS0_OFFSET) +#define S5P_PHYSTATUS1 S5P_DMC_BASE(PHYSTATUS1_OFFSET) +#define S5P_CHIP0STATUS S5P_DMC_BASE(CHIP0STATUS_OFFSET) +#define S5P_CHIP1STATUS S5P_DMC_BASE(CHIP1STATUS_OFFSET) +#define S5P_AREFSTATUS S5P_DMC_BASE(AREFSTATUS_OFFSET) +#define S5P_MRSTATUS S5P_DMC_BASE(MRSTATUS_OFFSET) +#define S5P_PHYTEST0 S5P_DMC_BASE(PHYTEST0_OFFSET) +#define S5P_PHYTEST1 S5P_DMC_BASE(PHYTEST1_OFFSET) + +#define S5P_QOSCONTROL0 S5P_DMC_BASE(QOSCONTROL0_OFFSET) +#define S5P_QOSCONFIG0 S5P_DMC_BASE(QOSCONFIG0_OFFSET) +#define S5P_QOSCONTROL1 S5P_DMC_BASE(QOSCONTROL1_OFFSET) +#define S5P_QOSCONFIG1 S5P_DMC_BASE(QOSCONFIG1_OFFSET) +#define S5P_QOSCONTROL2 S5P_DMC_BASE(QOSCONTROL2_OFFSET) +#define S5P_QOSCONFIG2 S5P_DMC_BASE(QOSCONFIG2_OFFSET) +#define S5P_QOSCONTROL3 S5P_DMC_BASE(QOSCONTROL3_OFFSET) +#define S5P_QOSCONFIG3 S5P_DMC_BASE(QOSCONFIG3_OFFSET) +#define S5P_QOSCONTROL4 S5P_DMC_BASE(QOSCONTROL4_OFFSET) +#define S5P_QOSCONFIG4 S5P_DMC_BASE(QOSCONFIG4_OFFSET) +#define S5P_QOSCONTROL5 S5P_DMC_BASE(QOSCONTROL5_OFFSET) +#define S5P_QOSCONFIG5 S5P_DMC_BASE(QOSCONFIG5_OFFSET) +#define S5P_QOSCONTROL6 S5P_DMC_BASE(QOSCONTROL6_OFFSET) +#define S5P_QOSCONFIG6 S5P_DMC_BASE(QOSCONFIG6_OFFSET) +#define S5P_QOSCONTROL7 S5P_DMC_BASE(QOSCONTROL7_OFFSET) +#define S5P_QOSCONFIG7 S5P_DMC_BASE(QOSCONFIG7_OFFSET) + + +/* SROM */ +#define S5P_SROMC_BASE(x) (S5P_PA_SROMC + (x)) + +#define SROM_BW_OFFSET 0x0 +#define SROM_BC0_OFFSET 0x04 +#define SROM_BC1_OFFSET 0x08 +#define SROM_BC2_OFFSET 0x0c +#define SROM_BC3_OFFSET 0x10 +#define SROM_BC4_OFFSET 0x14 +#define SROM_BC5_OFFSET 0x18 + +#define S5P_SROM_BW __REG(S5P_SROMC_BASE(SROM_BW_OFFSET)) +#define S5P_SROM_BC0 __REG(S5P_SROMC_BASE(SROM_BC0_OFFSET)) +#define S5P_SROM_BC1 S5P_SROMC_BASE(SROM_BC1_OFFSET) +#define S5P_SROM_BC2 S5P_SROMC_BASE(SROM_BC2_OFFSET) +#define S5P_SROM_BC3 S5P_SROMC_BASE(SROM_BC3_OFFSET) +#define S5P_SROM_BC4 S5P_SROMC_BASE(SROM_BC4_OFFSET) +#define S5P_SROM_BC5 S5P_SROMC_BASE(SROM_BC5_OFFSET) + + +/* OneNand */ +#define S5P_ONENANDC_BASE(x) (S5P_PA_ONENANDC + (x)) + +#define MEM_CFG_OFFSET 0x0 +#define BURST_LEN_OFFSET 0x10 +#define MEM_RESET_OFFSET 0x20 +#define INT_ERR_STAT_OFFSET 0x30 +#define INT_ERR_MASK_OFFSET 0x40 +#define INT_ERR_ACK_OFFSET 0x50 +#define ECC_ERR_STAT_1_OFFSET 0x60 +#define MANUFACT_ID_OFFSET 0x70 +#define DEVICE_ID_OFFSET 0x80 +#define DATA_BUF_SIZE_OFFSET 0x90 +#define BOOT_BUF_SIZE_OFFSET 0xa0 +#define BUF_AMOUNT_OFFSET 0xb0 +#define TECH_OFFSET 0xc0 +#define FBA_WIDTH_OFFSET 0xd0 +#define FPA_WIDTH_OFFSET 0xe0 +#define FSA_WIDTH_OFFSET 0xf0 +#define REVISION_OFFSET 0x100 +#define SYNC_MODE_OFFSET 0x130 +#define TRANS_SPARE_OFFSET 0x140 +#define PAGE_CNT_OFFSET 0x170 +#define ERR_PAGE_ADDR_OFFSET 0x180 +#define BURST_RD_LAT_OFFSET 0x190 +#define INT_PIN_ENABLE_OFFSET 0x1a0 +#define INT_MON_CYC_OFFSET 0x1b0 +#define ACC_CLOCK_OFFSET 0x1c0 +#define ERR_BLK_ADDR_OFFSET 0x1e0 +#define FLASH_VER_ID_OFFSET 0x1f0 +#define BANK_EN_OFFSET 0x220 +#define WTCHDG_RST_L_OFFSET 0x260 +#define WTCHDG_RST_H_OFFSET 0x270 +#define SYNC_WRITE_OFFSET 0x280 +#define CACHE_READ_OFFSET 0x290 +#define COLD_RST_DLY_OFFSET 0x2a0 +#define DDP_DEVICE_OFFSET 0x2b0 +#define MULTI_PLANE_OFFSET 0x2c0 +#define TRANS_MODE_OFFSET 0x2e0 +#define DEV_STAT_OFFSET 0x2f0 +#define ECC_ERR_STAT_2_OFFSET 0x300 +#define ECC_ERR_STAT_3_OFFSET 0x310 +#define ECC_ERR_STAT_4_OFFSET 0x320 +#define EFCT_BUF_CNT_OFFSET 0x330 +#define DEV_PAGE_SIZE_OFFSET 0x340 +#define SUPERLOAD_EN_OFFSET 0x350 +#define CACHE_PRG_EN_OFFSET 0x360 +#define SINGLE_PAGE_BUF_OFFSET 0x370 +#define OFFSET_ADDR_OFFSET 0x380 +#define INT_MON_STATUS_OFFSET 0x390 + +#define S5P_MEM_CFG S5P_ONENANDC_BASE(MEM_CFG_OFFSET) +#define S5P_BURST_LEN S5P_ONENANDC_BASE(BURST_LEN_OFFSET) +#define S5P_MEM_RESET S5P_ONENANDC_BASE(MEM_RESET_OFFSET) +#define S5P_INT_ERR_STAT S5P_ONENANDC_BASE(INT_ERR_STAT_OFFSET) +#define S5P_INT_ERR_MASK S5P_ONENANDC_BASE(INT_ERR_MASK_OFFSET) +#define S5P_INT_ERR_ACK S5P_ONENANDC_BASE(INT_ERR_ACK_OFFSET) +#define S5P_ECC_ERR_STAT_1 S5P_ONENANDC_BASE(ECC_ERR_STAT_1_OFFSET) +#define S5P_MANUFACT_ID S5P_ONENANDC_BASE(MANUFACT_ID_OFFSET) +#define S5P_DEVICE_ID S5P_ONENANDC_BASE(DEVICE_ID_OFFSET) +#define S5P_DATA_BUF_SIZE S5P_ONENANDC_BASE(DATA_BUF_SIZE_OFFSET) +#define S5P_BOOT_BUF_SIZE S5P_ONENANDC_BASE(BOOT_BUF_SIZE_OFFSET) +#define S5P_BUF_AMOUNT S5P_ONENANDC_BASE(BUF_AMOUNT_OFFSET) +#define S5P_TECH S5P_ONENANDC_BASE(TECH_OFFSET) +#define S5P_FBA_WIDTH S5P_ONENANDC_BASE(FBA_WIDTH_OFFSET) +#define S5P_FPA_WIDTH S5P_ONENANDC_BASE(FPA_WIDTH_OFFSET) +#define S5P_FSA_WIDTH S5P_ONENANDC_BASE(FSA_WIDTH_OFFSET) +#define S5P_REVISION S5P_ONENANDC_BASE(REVISION_OFFSET) +#define S5P_SYNC_MODE S5P_ONENANDC_BASE(SYNC_MODE_OFFSET) +#define S5P_TRANS_SPARE S5P_ONENANDC_BASE(TRANS_SPARE_OFFSET) +#define S5P_PAGE_CNT S5P_ONENANDC_BASE(PAGE_CNT_OFFSET) +#define S5P_ERR_PAGE_ADDR S5P_ONENANDC_BASE(ERR_PAGE_ADDR_OFFSET) +#define S5P_BURST_RD_LAT S5P_ONENANDC_BASE(BURST_RD_LAT_OFFSET) +#define S5P_INT_PIN_ENABLE S5P_ONENANDC_BASE(INT_PIN_ENABLE_OFFSET) +#define S5P_INT_MON_CYC S5P_ONENANDC_BASE(INT_MON_CYC_OFFSET) +#define S5P_ACC_CLOCK S5P_ONENANDC_BASE(ACC_CLOCK_OFFSET) +#define S5P_ERR_BLK_ADDR S5P_ONENANDC_BASE(ERR_BLK_ADDR_OFFSET) +#define S5P_FLASH_VER_ID S5P_ONENANDC_BASE(FLASH_VER_ID_OFFSET) +#define S5P_BANK_EN S5P_ONENANDC_BASE(BANK_EN_OFFSET) +#define S5P_WTCHDG_RST_L S5P_ONENANDC_BASE(WTCHDG_RST_L_OFFSET) +#define S5P_WTCHDG_RST_H S5P_ONENANDC_BASE(WTCHDG_RST_H_OFFSET) +#define S5P_SYNC_WRITE S5P_ONENANDC_BASE(SYNC_WRITE_OFFSET) +#define S5P_CACHE_READ S5P_ONENANDC_BASE(CACHE_READ_OFFSET) +#define S5P_COLD_RST_DLY S5P_ONENANDC_BASE(COLD_RST_DLY_OFFSET) +#define S5P_DDP_DEVICE S5P_ONENANDC_BASE(DDP_DEVICE_OFFSET) +#define S5P_MULTI_PLANE S5P_ONENANDC_BASE(MULTI_PLANE_OFFSET) +#define S5P_MEM_CNT S5P_ONENANDC_BASE(MEM_CNT_OFFSET) +#define S5P_TRANS_MODE S5P_ONENANDC_BASE(TRANS_MODE_OFFSET) +#define S5P_DEV_START S5P_ONENANDC_BASE(DEV_START_OFFSET) +#define S5P_ECC_ERR_STAT_2 S5P_ONENANDC_BASE(ECC_ERR_STAT_2_OFFSET) +#define S5P_ECC_ERR_STAT_3 S5P_ONENANDC_BASE(ECC_ERR_STAT_3_OFFSET) +#define S5P_ECC_ERR_STAT_4 S5P_ONENANDC_BASE(ECC_ERR_STAT_4_OFFSET) +#define S5P_EFCT_BUF_CNT S5P_ONENANDC_BASE(EFCT_BUF_CNT_OFFSET) +#define S5P_DEV_PAGE_SIZE S5P_ONENANDC_BASE(DEV_PAGE_SIZE_OFFSET) +#define S5P_SUPERLOAD_EN S5P_ONENANDC_BASE(SUPERLOAD_EN_OFFSET) +#define S5P_CACHE_PRG_EN S5P_ONENANDC_BASE(CACHE_PRG_EN_OFFSET) +#define S5P_SINGLE_PAGE_BUF S5P_ONENANDC_BASE(SINGLE_PAGE_BUF_OFFSET) +#define S5P_OFFSET_ADDR S5P_ONENANDC_BASE(OFFSET_ADDR_OFFSET) +#define S5P_INT_MON_STATUS S5P_ONENANDC_BASE(INT_MON_STATUS_OFFSET) + + + /* * Timer * : PWM, Watchdog, System timer, RTC */ +/* PWM */ +#define S5P_PWMTIMER_BASE(x) (S5P_PA_PWMTIMER + (x)) + +#define PWM_TCFG0_OFFSET 0x0 +#define PWM_TCFG1_OFFSET 0x04 +#define PWM_TCON_OFFSET 0x08 +#define PWM_TCNTB0_OFFSET 0x0c +#define PWM_TCMPB0_OFFSET 0x10 +#define PWM_TCNTO0_OFFSET 0x14 +#define PWM_TCNTB1_OFFSET 0x18 +#define PWM_TCMPB1_OFFSET 0x1c +#define PWM_TCNTO1_OFFSET 0x20 +#define PWM_TCNTB2_OFFSET 0x24 +#define PWM_TCMPB2_OFFSET 0x28 +#define PWM_TCNTO2_OFFSET 0x2c +#define PWM_TCNTB3_OFFSET 0x30 +#define PWM_TCNTO3_OFFSET 0x38 +#define PWM_TCNTB4_OFFSET 0x3c +#define PWM_TCNTO4_OFFSET 0x40 +#define PWM_TINT_CSTAT_OFFSET 0x44 + +#define S5P_PWM_TCFG0 S5P_PWMTIMER_BASE(PWM_TCFG0_OFFSET) +#define S5P_PWM_TCFG1 S5P_PWMTIMER_BASE(PWM_TCFG1_OFFSET) +#define S5P_PWM_TCON S5P_PWMTIMER_BASE(PWM_TCON_OFFSET) +#define S5P_PWM_TCNTB0 S5P_PWMTIMER_BASE(PWM_TCNTB0_OFFSET) +#define S5P_PWM_TCMPB0 S5P_PWMTIMER_BASE(PWM_TCMPB0_OFFSET) +#define S5P_PWM_TCNTO0 S5P_PWMTIMER_BASE(PWM_TCNTO0_OFFSET) +#define S5P_PWM_TCNTB1 S5P_PWMTIMER_BASE(PWM_TCNTB1_OFFSET) +#define S5P_PWM_TCMPB1 S5P_PWMTIMER_BASE(PWM_TCMPB1_OFFSET) +#define S5P_PWM_TCNTO1 S5P_PWMTIMER_BASE(PWM_TCNTO1_OFFSET) +#define S5P_PWM_TCNTB2 S5P_PWMTIMER_BASE(PWM_TCNTB2_OFFSET) +#define S5P_PWM_TCMPB2 S5P_PWMTIMER_BASE(PWM_TCMPB2_OFFSET) +#define S5P_PWM_TCNTO2 S5P_PWMTIMER_BASE(PWM_TCNTO2_OFFSET) +#define S5P_PWM_TCNTB3 S5P_PWMTIMER_BASE(PWM_TCNTB3_OFFSET) +#define S5P_PWM_TCNTO3 S5P_PWMTIMER_BASE(PWM_TCNTO3_OFFSET) +#define S5P_PWM_TCNTB4 S5P_PWMTIMER_BASE(PWM_TCNTB4_OFFSET) +#define S5P_PWM_TCNTO4 S5P_PWMTIMER_BASE(PWM_TCNTO4_OFFSET) +#define S5P_PWM_TINT_CSTAT S5P_PWMTIMER_BASE(PWM_TINT_CSTAT_OFFSET) + + +/* System Timer */ +#define S5P_SYSTIMER_BASE(x) (S5P_PA_SYSTEM + (x)) + +#define SYS_TCFG_OFFSET 0x0 +#define SYS_TCON_OFFSET 0x04 +#define SYS_TCNTB_OFFSET 0x08 +#define SYS_TCNTO_OFFSET 0x0c +#define SYS_ICNTB_OFFSET 0x10 +#define SYS_ICNTO_OFFSET 0x14 +#define SYS_INT_CSTAT_OFFSET 0x18 + +#define S5P_SYS_TCFG S5P_SYSTIMER_BASE(SYS_TCFG_OFFSET) +#define S5P_SYS_TCON S5P_SYSTIMER_BASE(SYS_TCON_OFFSET) +#define S5P_SYS_TCNTB S5P_SYSTIMER_BASE(SYS_TCNTB_OFFSET) +#define S5P_SYS_TCNTO S5P_SYSTIMER_BASE(SYS_TCNTO_OFFSET) +#define S5P_SYS_ICNTB S5P_SYSTIMER_BASE(SYS_ICNTB_OFFSET) +#define S5P_SYS_ICNTO S5P_SYSTIMER_BASE(SYS_ICNTO_OFFSET) +#define S5P_SYS_INT_CSTAT S5P_SYSTIMER_BASE(SYS_INT_CSTAT_OFFSET) + + +/* Watchdog */ +#define S5P_WATCHDOG_BASE(x) (S5P_PA_WATCHDOG + (x)) + +#define WTCON_OFFSET 0x0 +#define WTDAT_OFFSET 0x4 +#define WTCNT_OFFSET 0x8 +#define WTCLRINT_OFFSET 0xc + +#define S5P_WTCON S5P_WATCHDOG_BASE(WTCON_OFFSET) +#define S5P_WTDAT S5P_WATCHDOG_BASE(WTDAT_OFFSET) +#define S5P_WTCNT S5P_WATCHDOG_BASE(WTCNT_OFFSET) +#define S5P_WTCLRINT S5P_WATCHDOG_BASE(WTCLRINT_OFFSET) + + +/* RTC */ +#define S5P_RTC_BASE(x) (S5P_PA_RTC + (x)) + +#define INTP_OFFSET 0x30 +#define RTCCON_OFFSET 0x40 +#define TICCNT_OFFSET 0x44 +#define RTCALM_OFFSET 0x50 + +#define ALMSEC_OFFSET 0x54 +#define ALMMIN_OFFSET 0x58 +#define ALMHOUR_OFFSET 0x5c +#define ALMDATE_OFFSET 0x60 +#define ALMMON_OFFSET 0x64 +#define ALMYEAR_OFFSET 0x68 + +#define BCDSEC_OFFSET 0x70 +#define BCDMIN_OFFSET 0x74 +#define BCDHOUR_OFFSET 0x78 +#define BCDDATE_OFFSET 0x7c +#define BCDDAY_OFFSET 0x80 +#define BCDMON_OFFSET 0x84 +#define BCDYEAR_OFFSET 0x88 + +#define CURTICCNT 0x90 + + + + +#define S5P_INTP S5P_RTC_BASE(INTP_OFFSET) +#define S5P_RTCCON S5P_RTC_BASE(RTCCON_OFFSET) +#define S5P_TICCNT S5P_RTC_BASE(TICCNT_OFFSET) +#define S5P_RTCALM S5P_RTC_BASE(RTCALM_OFFSET) + +#define S5P_ALMSEC S5P_RTC_BASE(ALMSEC_OFFSET) +#define S5P_ALMMIN S5P_RTC_BASE(ALMMIN_FFSET) +#define S5P_ALMHOUR S5P_RTC_BASE(ALMHOUR_OFFSET) +#define S5P_ALMDATE S5P_RTC_BASE(ALMDATE_OFFSET) +#define S5P_ALMMON S5P_RTC_BASE(ALMMON_OFFSET) +#define S5P_ALMYEAR S5P_RTC_BASE(ALMYEAR_OFFSET) + +#define S5P_BCDSEC S5P_RTC_BASE(BCDSEC_OFFSET) +#define S5P_BCDMIN S5P_RTC_BASE(BCDMIN_OFFSET) +#define S5P_BCDHOUR S5P_RTC_BASE(BCDHOUR_OFFSET) +#define S5P_BCDDATE S5P_RTC_BASE(BCDDATE_OFFSET) +#define S5P_BCDDAY S5P_RTC_BASE(BCDDAY_OFFSET) +#define S5P_BCDMON S5P_RTC_BASE(BCDMON_OFFSET) +#define S5P_BCDYEAR S5P_RTC_BASE(BCDYEAR_OFFSET) + +#define S5P_CURTICCNT S5P_RTC_BASE(CURTICCNT_OFFSET) /* @@ -1068,7 +1483,8 @@ #define S5P_PA_UART S5P_ADDR(0x0c000000) /* UART */ -#endif /*__S5PC100_H__*/ +//#endif /*__S5PC100_H__*/ + diff --git a/lib_arm/board.c b/lib_arm/board.c index b7f88a0..0808285 100644 --- a/lib_arm/board.c +++ b/lib_arm/board.c @@ -285,7 +285,7 @@ init_fnc_t *init_sequence[] = { #if defined(CONFIG_CMD_PCI) || defined (CONFIG_PCI) arm_pci_init, #endif - display_dram_config, + //display_dram_config, NULL, }; @@ -318,7 +318,7 @@ void start_armboot (void) #ifndef CONFIG_SYS_NO_FLASH /* configure available FLASH banks */ - display_flash_config (flash_init ()); + //display_flash_config (flash_init ()); #endif /* CONFIG_SYS_NO_FLASH */ #ifdef CONFIG_VFD @@ -355,24 +355,24 @@ void start_armboot (void) #if defined(CONFIG_CMD_NAND) puts ("NAND: "); - nand_init(); /* go init the NAND */ + //nand_init(); /* go init the NAND */ #endif #if defined(CONFIG_CMD_ONENAND) - onenand_init(); + //onenand_init(); #endif #ifdef CONFIG_HAS_DATAFLASH - AT91F_DataflashInit(); - dataflash_print_info(); + //AT91F_DataflashInit(); + //dataflash_print_info(); #endif /* initialize environment */ - env_relocate (); + //env_relocate (); #ifdef CONFIG_VFD /* must do this after the framebuffer is allocated */ - drv_vfd_init(); + //drv_vfd_init(); #endif /* CONFIG_VFD */ #ifdef CONFIG_SERIAL_MULTI @@ -380,18 +380,18 @@ void start_armboot (void) #endif /* IP Address */ - gd->bd->bi_ip_addr = getenv_IPaddr ("ipaddr"); + //gd->bd->bi_ip_addr = getenv_IPaddr ("ipaddr"); - devices_init (); /* get the devices list going. */ + //devices_init (); /* get the devices list going. */ - jumptable_init (); + //jumptable_init (); #if defined(CONFIG_API) /* Initialize API */ - api_init (); + //api_init (); #endif - console_init_r (); /* fully init console as a device */ + //console_init_r (); /* fully init console as a device */ #if defined(CONFIG_MISC_INIT_R) /* miscellaneous platform dependent initialisations */ @@ -400,54 +400,62 @@ void start_armboot (void) #endif /* enable exceptions */ - enable_interrupts (); + //enable_interrupts (); /* Perform network card initialisation if necessary */ #ifdef CONFIG_DRIVER_TI_EMAC /* XXX: this needs to be moved to board init */ + /* extern void davinci_eth_set_mac_addr (const u_int8_t *addr); if (getenv ("ethaddr")) { uchar enetaddr[6]; eth_getenv_enetaddr("ethaddr", enetaddr); davinci_eth_set_mac_addr(enetaddr); } + */ #endif #ifdef CONFIG_DRIVER_CS8900 /* XXX: this needs to be moved to board init */ - cs8900_get_enetaddr (); + //cs8900_get_enetaddr (); #endif #if defined(CONFIG_DRIVER_SMC91111) || defined (CONFIG_DRIVER_LAN91C96) /* XXX: this needs to be moved to board init */ + /* if (getenv ("ethaddr")) { uchar enetaddr[6]; eth_getenv_enetaddr("ethaddr", enetaddr); smc_set_mac_addr(enetaddr); } + */ #endif /* CONFIG_DRIVER_SMC91111 || CONFIG_DRIVER_LAN91C96 */ /* Initialize from environment */ + /* if ((s = getenv ("loadaddr")) != NULL) { load_addr = simple_strtoul (s, NULL, 16); } + */ #if defined(CONFIG_CMD_NET) + /* if ((s = getenv ("bootfile")) != NULL) { copy_filename (BootFile, s, sizeof (BootFile)); } + */ #endif #ifdef BOARD_LATE_INIT - board_late_init (); + //board_late_init (); #endif #if defined(CONFIG_CMD_NET) #if defined(CONFIG_NET_MULTI) puts ("Net: "); #endif - eth_initialize(gd->bd); + //eth_initialize(gd->bd); #if defined(CONFIG_RESET_PHY_R) debug ("Reset Ethernet PHY\n"); - reset_phy(); + //reset_phy(); #endif #endif /* main_loop() can return to retry autoboot, if so just run it again. */