From: Koji Matsuoka Date: Mon, 18 Apr 2016 07:31:30 +0000 (+0900) Subject: drm: rcar-du: Fix display timing controller parameter X-Git-Tag: v4.14-rc1~1925^2~31^2~2 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=9cdced8a39c04cf798ddb2a27cb5952f7d39f633;p=platform%2Fkernel%2Flinux-rpi.git drm: rcar-du: Fix display timing controller parameter There is a bug in the setting of the DES (Display Enable Signal) register. This current setting occurs 1 dot left shift. The DES register should be set minus one value about the specifying value with H/W specification. This patch corrects it. Signed-off-by: Koji Matsuoka Signed-off-by: Laurent Pinchart --- diff --git a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c index 7316fc7..aca26ee 100644 --- a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c +++ b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c @@ -172,7 +172,7 @@ static void rcar_du_crtc_set_display_timing(struct rcar_du_crtc *rcrtc) mode->crtc_vsync_start - 1); rcar_du_crtc_write(rcrtc, VCR, mode->crtc_vtotal - 1); - rcar_du_crtc_write(rcrtc, DESR, mode->htotal - mode->hsync_start); + rcar_du_crtc_write(rcrtc, DESR, mode->htotal - mode->hsync_start - 1); rcar_du_crtc_write(rcrtc, DEWR, mode->hdisplay); }