From: Dmitry Preobrazhensky <dmitry.preobrazhensky@amd.com>
Date: Mon, 2 Sep 2019 13:42:25 +0000 (+0000)
Subject: [AMDGPU][MC][GFX10] Enabled null with 64-bit operands
X-Git-Tag: llvmorg-11-init~10248
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=9c68eddbbe77c7d136de1ec23ed232d3042b0505;p=platform%2Fupstream%2Fllvm.git

[AMDGPU][MC][GFX10] Enabled null with 64-bit operands

See Bug 42745: https://bugs.llvm.org/show_bug.cgi?id=42745

Reviewers: atamazov, arsenm

https://reviews.llvm.org/D65231

llvm-svn: 370660
---

diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
index ab9e0a9..519f809 100644
--- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
@@ -1854,6 +1854,8 @@ static bool isInlineValue(unsigned Reg) {
   case AMDGPU::SRC_EXECZ:
   case AMDGPU::SRC_SCC:
     return true;
+  case AMDGPU::SGPR_NULL:
+    return true;
   default:
     return false;
   }
diff --git a/llvm/test/MC/AMDGPU/reg-syntax-extra.s b/llvm/test/MC/AMDGPU/reg-syntax-extra.s
index 18a6dab..4e8216c 100644
--- a/llvm/test/MC/AMDGPU/reg-syntax-extra.s
+++ b/llvm/test/MC/AMDGPU/reg-syntax-extra.s
@@ -116,6 +116,14 @@ v_mul_f32 v0, null, v2
 // NOSICIVI: error:
 // GFX10: v_mul_f32_e32 v0, null, v2      ; encoding: [0x7d,0x04,0x00,0x10]
 
+v_mul_f64 v[0:1], null, null
+// NOSICIVI: error:
+// GFX10: v_mul_f64 v[0:1], null, null    ; encoding: [0x00,0x00,0x65,0xd5,0x7d,0xfa,0x00,0x00]
+
 s_add_u32 null, null, null
 // NOSICIVI: error:
 // GFX10: s_add_u32 null, null, null      ; encoding: [0x7d,0x7d,0x7d,0x80]
+
+s_not_b64 s[2:3], null
+// NOSICIVI: error:
+// GFX10: s_not_b64 s[2:3], null          ; encoding: [0x7d,0x08,0x82,0xbe]