From: Jack Carter Date: Tue, 5 Feb 2013 08:32:10 +0000 (+0000) Subject: This patch that sets the EmitAlias flag in td files X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=9c1a027fe884c11f0302534edbc6320f8c83999d;p=platform%2Fupstream%2Fllvm.git This patch that sets the EmitAlias flag in td files and enables the instruction printer to print aliased instructions. Due to usage of RegisterOperands a change in common code (utils/TableGen/AsmWriterEmitter.cpp) is required to get the correct register value if it is a RegisterOperand. Contributer: Vladimir Medic llvm-svn: 174358 --- diff --git a/llvm/lib/Target/Mips/InstPrinter/MipsInstPrinter.cpp b/llvm/lib/Target/Mips/InstPrinter/MipsInstPrinter.cpp index 97c367f..fc23cd3 100644 --- a/llvm/lib/Target/Mips/InstPrinter/MipsInstPrinter.cpp +++ b/llvm/lib/Target/Mips/InstPrinter/MipsInstPrinter.cpp @@ -23,6 +23,7 @@ #include "llvm/Support/raw_ostream.h" using namespace llvm; +#define PRINT_ALIAS_INSTR #include "MipsGenAsmWriter.inc" const char* Mips::MipsFCCToString(Mips::CondCode CC) { @@ -78,7 +79,9 @@ void MipsInstPrinter::printInst(const MCInst *MI, raw_ostream &O, O << "\t.set\tmips32r2\n"; } - printInstruction(MI, O); + // Try to print any aliases first. + if (!printAliasInstr(MI, O)) + printInstruction(MI, O); printAnnotation(O, Annot); switch (MI->getOpcode()) { diff --git a/llvm/lib/Target/Mips/InstPrinter/MipsInstPrinter.h b/llvm/lib/Target/Mips/InstPrinter/MipsInstPrinter.h index 38cac68..d1b561f 100644 --- a/llvm/lib/Target/Mips/InstPrinter/MipsInstPrinter.h +++ b/llvm/lib/Target/Mips/InstPrinter/MipsInstPrinter.h @@ -89,6 +89,8 @@ public: virtual void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot); void printCPURegs(const MCInst *MI, unsigned OpNo, raw_ostream &O); + bool printAliasInstr(const MCInst *MI, raw_ostream &OS); + private: void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O); void printUnsignedImm(const MCInst *MI, int opNum, raw_ostream &O); diff --git a/llvm/lib/Target/Mips/Mips64InstrInfo.td b/llvm/lib/Target/Mips/Mips64InstrInfo.td index 2b2c6b7..db92c64 100644 --- a/llvm/lib/Target/Mips/Mips64InstrInfo.td +++ b/llvm/lib/Target/Mips/Mips64InstrInfo.td @@ -308,26 +308,33 @@ def : MipsPat<(bswap CPU64Regs:$rt), (DSHD (DSBH CPU64Regs:$rt))>; //===----------------------------------------------------------------------===// // Instruction aliases //===----------------------------------------------------------------------===// -def : InstAlias<"move $dst, $src", (DADDu CPU64RegsOpnd:$dst, - CPU64RegsOpnd:$src,ZERO_64)>, +def : InstAlias<"move $dst, $src", + (DADDu CPU64RegsOpnd:$dst, CPU64RegsOpnd:$src, ZERO_64), 1>, + Requires<[HasMips64]>; +def : InstAlias<"move $dst, $src", + (OR64 CPU64RegsOpnd:$dst, CPU64RegsOpnd:$src, ZERO_64), 0>, Requires<[HasMips64]>; def : InstAlias<"and $rs, $rt, $imm", - (DANDi CPU64RegsOpnd:$rs, CPU64RegsOpnd:$rt, uimm16_64:$imm)>, + (DANDi CPU64RegsOpnd:$rs, CPU64RegsOpnd:$rt, uimm16_64:$imm), + 1>, Requires<[HasMips64]>; def : InstAlias<"slt $rs, $rt, $imm", - (SLTi64 CPURegsOpnd:$rs, CPU64Regs:$rt, simm16_64:$imm)>, + (SLTi64 CPURegsOpnd:$rs, CPU64Regs:$rt, simm16_64:$imm), 1>, Requires<[HasMips64]>; def : InstAlias<"xor $rs, $rt, $imm", - (XORi64 CPU64RegsOpnd:$rs, CPU64RegsOpnd:$rt, uimm16_64:$imm)>, + (XORi64 CPU64RegsOpnd:$rs, CPU64RegsOpnd:$rt, uimm16_64:$imm), + 1>, Requires<[HasMips64]>; def : InstAlias<"not $rt, $rs", - (NOR64 CPU64RegsOpnd:$rt, CPU64RegsOpnd:$rs, ZERO_64)>, + (NOR64 CPU64RegsOpnd:$rt, CPU64RegsOpnd:$rs, ZERO_64), 1>, Requires<[HasMips64]>; -def : InstAlias<"j $rs", (JR64 CPU64Regs:$rs)>, Requires<[HasMips64]>; +def : InstAlias<"j $rs", (JR64 CPU64Regs:$rs), 0>, Requires<[HasMips64]>; def : InstAlias<"daddu $rs, $rt, $imm", - (DADDiu CPU64RegsOpnd:$rs, CPU64RegsOpnd:$rt, simm16_64:$imm)>; + (DADDiu CPU64RegsOpnd:$rs, CPU64RegsOpnd:$rt, simm16_64:$imm), + 1>; def : InstAlias<"dadd $rs, $rt, $imm", - (DADDi CPU64RegsOpnd:$rs, CPU64RegsOpnd:$rt, simm16_64:$imm)>; + (DADDi CPU64RegsOpnd:$rs, CPU64RegsOpnd:$rt, simm16_64:$imm), + 1>; /// Move between CPU and coprocessor registers @@ -348,11 +355,11 @@ def DMTC2_3OP64 : MFC3OP<(outs CPU64RegsOpnd:$rd, uimm16:$sel), // Two operand (implicit 0 selector) versions: def : InstAlias<"dmfc0 $rt, $rd", - (DMFC0_3OP64 CPU64RegsOpnd:$rt, CPU64RegsOpnd:$rd, 0)>; + (DMFC0_3OP64 CPU64RegsOpnd:$rt, CPU64RegsOpnd:$rd, 0), 0>; def : InstAlias<"dmtc0 $rt, $rd", - (DMTC0_3OP64 CPU64RegsOpnd:$rd, 0, CPU64RegsOpnd:$rt)>; + (DMTC0_3OP64 CPU64RegsOpnd:$rd, 0, CPU64RegsOpnd:$rt), 0>; def : InstAlias<"dmfc2 $rt, $rd", - (DMFC2_3OP64 CPU64RegsOpnd:$rt, CPU64RegsOpnd:$rd, 0)>; + (DMFC2_3OP64 CPU64RegsOpnd:$rt, CPU64RegsOpnd:$rd, 0), 0>; def : InstAlias<"dmtc2 $rt, $rd", - (DMTC2_3OP64 CPU64RegsOpnd:$rd, 0, CPU64RegsOpnd:$rt)>; + (DMTC2_3OP64 CPU64RegsOpnd:$rd, 0, CPU64RegsOpnd:$rt), 0>; diff --git a/llvm/lib/Target/Mips/MipsInstrInfo.td b/llvm/lib/Target/Mips/MipsInstrInfo.td index ac99a13..b563b8f 100644 --- a/llvm/lib/Target/Mips/MipsInstrInfo.td +++ b/llvm/lib/Target/Mips/MipsInstrInfo.td @@ -957,33 +957,41 @@ def MTC2_3OP : MFC3OP<(outs CPURegsOpnd:$rd, uimm16:$sel), //===----------------------------------------------------------------------===// // Instruction aliases //===----------------------------------------------------------------------===// -def : InstAlias<"move $dst,$src", (ADDu CPURegsOpnd:$dst, - CPURegsOpnd:$src,ZERO)>, Requires<[NotMips64]>; -def : InstAlias<"bal $offset", (BGEZAL RA, brtarget:$offset)>; +def : InstAlias<"move $dst, $src", + (ADDu CPURegsOpnd:$dst, CPURegsOpnd:$src,ZERO), 1>, + Requires<[NotMips64]>; +def : InstAlias<"move $dst, $src", + (OR CPURegsOpnd:$dst, CPURegsOpnd:$src,ZERO), 0>, + Requires<[NotMips64]>; +def : InstAlias<"bal $offset", (BGEZAL RA, brtarget:$offset), 1>; def : InstAlias<"addu $rs, $rt, $imm", - (ADDiu CPURegsOpnd:$rs, CPURegsOpnd:$rt, simm16:$imm)>; + (ADDiu CPURegsOpnd:$rs, CPURegsOpnd:$rt, simm16:$imm), 0>; def : InstAlias<"add $rs, $rt, $imm", - (ADDi CPURegsOpnd:$rs, CPURegsOpnd:$rt, simm16:$imm)>; + (ADDi CPURegsOpnd:$rs, CPURegsOpnd:$rt, simm16:$imm), 0>; def : InstAlias<"and $rs, $rt, $imm", - (ANDi CPURegsOpnd:$rs, CPURegsOpnd:$rt, simm16:$imm)>; -def : InstAlias<"j $rs", (JR CPURegs:$rs)>, Requires<[NotMips64]>; -def : InstAlias<"not $rt, $rs", (NOR CPURegsOpnd:$rt, CPURegsOpnd:$rs, ZERO)>; -def : InstAlias<"neg $rt, $rs", (SUB CPURegsOpnd:$rt, ZERO, CPURegsOpnd:$rs)>; -def : InstAlias<"negu $rt, $rs", (SUBu CPURegsOpnd:$rt, ZERO, - CPURegsOpnd:$rs)>; + (ANDi CPURegsOpnd:$rs, CPURegsOpnd:$rt, simm16:$imm), 0>; +def : InstAlias<"j $rs", (JR CPURegs:$rs), 0>, + Requires<[NotMips64]>; +def : InstAlias<"not $rt, $rs", + (NOR CPURegsOpnd:$rt, CPURegsOpnd:$rs, ZERO), 1>; +def : InstAlias<"neg $rt, $rs", + (SUB CPURegsOpnd:$rt, ZERO, CPURegsOpnd:$rs), 1>; +def : InstAlias<"negu $rt, $rs", + (SUBu CPURegsOpnd:$rt, ZERO, CPURegsOpnd:$rs), 1>; def : InstAlias<"slt $rs, $rt, $imm", - (SLTi CPURegsOpnd:$rs, CPURegs:$rt, simm16:$imm)>; + (SLTi CPURegsOpnd:$rs, CPURegs:$rt, simm16:$imm), 0>; def : InstAlias<"xor $rs, $rt, $imm", - (XORi CPURegsOpnd:$rs, CPURegsOpnd:$rt, simm16:$imm)>, - Requires<[NotMips64]>; -def : InstAlias<"mfc0 $rt, $rd", (MFC0_3OP CPURegsOpnd:$rt, - CPURegsOpnd:$rd, 0)>; -def : InstAlias<"mtc0 $rt, $rd", (MTC0_3OP CPURegsOpnd:$rd, 0, - CPURegsOpnd:$rt)>; -def : InstAlias<"mfc2 $rt, $rd", (MFC2_3OP CPURegsOpnd:$rt, - CPURegsOpnd:$rd, 0)>; -def : InstAlias<"mtc2 $rt, $rd", (MTC2_3OP CPURegsOpnd:$rd, 0, - CPURegsOpnd:$rt)>; + (XORi CPURegsOpnd:$rs, CPURegsOpnd:$rt, simm16:$imm), 0>, + Requires<[NotMips64]>; +def : InstAlias<"nop", (SLL ZERO, ZERO, 0), 1>; +def : InstAlias<"mfc0 $rt, $rd", + (MFC0_3OP CPURegsOpnd:$rt, CPURegsOpnd:$rd, 0), 0>; +def : InstAlias<"mtc0 $rt, $rd", + (MTC0_3OP CPURegsOpnd:$rd, 0, CPURegsOpnd:$rt), 0>; +def : InstAlias<"mfc2 $rt, $rd", + (MFC2_3OP CPURegsOpnd:$rt, CPURegsOpnd:$rd, 0), 0>; +def : InstAlias<"mtc2 $rt, $rd", + (MTC2_3OP CPURegsOpnd:$rd, 0, CPURegsOpnd:$rt), 0>; //===----------------------------------------------------------------------===// // Assembler Pseudo Instructions diff --git a/llvm/test/CodeGen/Mips/frame-address.ll b/llvm/test/CodeGen/Mips/frame-address.ll index e64e6d8..9b9ee21 100644 --- a/llvm/test/CodeGen/Mips/frame-address.ll +++ b/llvm/test/CodeGen/Mips/frame-address.ll @@ -7,6 +7,6 @@ entry: %0 = call i8* @llvm.frameaddress(i32 0) ret i8* %0 -; CHECK: addu $fp, $sp, $zero -; CHECK: or $2, $fp, $zero +; CHECK: move $fp, $sp +; CHECK: or $2, $fp, $zero } diff --git a/llvm/test/MC/Mips/mips-alu-instructions.s b/llvm/test/MC/Mips/mips-alu-instructions.s index 52fd900..816138e 100644 --- a/llvm/test/MC/Mips/mips-alu-instructions.s +++ b/llvm/test/MC/Mips/mips-alu-instructions.s @@ -31,7 +31,7 @@ # CHECK: xori $9, $6, 17767 # encoding: [0x67,0x45,0xc9,0x38] # CHECK: xori $9, $6, 17767 # encoding: [0x67,0x45,0xc9,0x38] # CHECK: wsbh $6, $7 # encoding: [0xa0,0x30,0x07,0x7c] -# CHECK: nor $7, $8, $zero # encoding: [0x27,0x38,0x00,0x01] +# CHECK: not $7, $8 # encoding: [0x27,0x38,0x00,0x01] and $9, $6, $7 and $9, $6, 17767 andi $9, $6, 17767 @@ -78,9 +78,9 @@ # CHECK: multu $3, $5 # encoding: [0x19,0x00,0x65,0x00] # CHECK: sub $9, $6, $7 # encoding: [0x22,0x48,0xc7,0x00] # CHECK: subu $4, $3, $5 # encoding: [0x23,0x20,0x65,0x00] -# CHECK: sub $6, $zero, $7 # encoding: [0x22,0x30,0x07,0x00] -# CHECK: subu $6, $zero, $7 # encoding: [0x23,0x30,0x07,0x00] -# CHECK: addu $7, $8, $zero # encoding: [0x21,0x38,0x00,0x01] +# CHECK: neg $6, $7 # encoding: [0x22,0x30,0x07,0x00] +# CHECK: negu $6, $7 # encoding: [0x23,0x30,0x07,0x00] +# CHECK: move $7, $8 # encoding: [0x21,0x38,0x00,0x01] # CHECK: .set push # CHECK: .set mips32r2 # CHECK: rdhwr $5, $29 diff --git a/llvm/test/MC/Mips/mips64-alu-instructions.s b/llvm/test/MC/Mips/mips64-alu-instructions.s index d30ddee..1b4ebdf 100644 --- a/llvm/test/MC/Mips/mips64-alu-instructions.s +++ b/llvm/test/MC/Mips/mips64-alu-instructions.s @@ -31,7 +31,7 @@ # CHECK: xori $9, $6, 17767 # encoding: [0x67,0x45,0xc9,0x38] # CHECK: xori $9, $6, 17767 # encoding: [0x67,0x45,0xc9,0x38] # CHECK: wsbh $6, $7 # encoding: [0xa0,0x30,0x07,0x7c] -# CHECK: nor $7, $8, $zero # encoding: [0x27,0x38,0x00,0x01] +# CHECK: not $7, $8 # encoding: [0x27,0x38,0x00,0x01] and $9, $6, $7 and $9, $6, 17767 andi $9, $6, 17767 @@ -76,11 +76,11 @@ # CHECK: msubu $6, $7 # encoding: [0x05,0x00,0xc7,0x70] # CHECK: mult $3, $5 # encoding: [0x18,0x00,0x65,0x00] # CHECK: multu $3, $5 # encoding: [0x19,0x00,0x65,0x00] -# CHECK: dsubu $4, $3, $5 # encoding: [0x2f,0x20,0x65,0x00] -# CHECK: daddu $7, $8, $zero # encoding: [0x2d,0x38,0x00,0x01] -# CHECK: .set push -# CHECK: .set mips32r2 -# CHECK: rdhwr $5, $29 +# CHECK: dsubu $4, $3, $5 # encoding: [0x2f,0x20,0x65,0x00] +# CHECK: move $7, $8 # encoding: [0x2d,0x38,0x00,0x01] +# CHECK: .set push +# CHECK: .set mips32r2 +# CHECK: rdhwr $5, $29 # CHECK: .set pop # encoding: [0x3b,0xe8,0x05,0x7c] dadd $9,$6,$7 diff --git a/llvm/utils/TableGen/AsmWriterEmitter.cpp b/llvm/utils/TableGen/AsmWriterEmitter.cpp index 73b083b..ac8d896 100644 --- a/llvm/utils/TableGen/AsmWriterEmitter.cpp +++ b/llvm/utils/TableGen/AsmWriterEmitter.cpp @@ -842,8 +842,11 @@ void AsmWriterEmitter::EmitPrintAliasInstruction(raw_ostream &O) { if (!IAP->isOpMapped(ROName)) { IAP->addOperand(ROName, i); + Record *R = CGA->ResultOperands[i].getRecord(); + if (R->isSubClassOf("RegisterOperand")) + R = R->getValueAsDef("RegClass"); Cond = std::string("MRI.getRegClass(") + Target.getName() + "::" + - CGA->ResultOperands[i].getRecord()->getName() + "RegClassID)" + R->getName() + "RegClassID)" ".contains(MI->getOperand(" + llvm::utostr(i) + ").getReg())"; IAP->addCond(Cond); } else {