From: Simon Pilgrim <llvm-dev@redking.me.uk>
Date: Tue, 1 Mar 2016 21:58:50 +0000 (+0000)
Subject: [X86][XOP] Regenerated intrinsics tests
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=9c03d1313c00995b80afc80b5e7fc1146d3d5914;p=platform%2Fupstream%2Fllvm.git

[X86][XOP] Regenerated intrinsics tests

llvm-svn: 262410
---

diff --git a/llvm/test/CodeGen/X86/xop-intrinsics-x86_64.ll b/llvm/test/CodeGen/X86/xop-intrinsics-x86_64.ll
index 3b4c6ea..c79c572 100644
--- a/llvm/test/CodeGen/X86/xop-intrinsics-x86_64.ll
+++ b/llvm/test/CodeGen/X86/xop-intrinsics-x86_64.ll
@@ -1,20 +1,28 @@
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -march=x86-64 -mattr=+avx,+fma4,+xop | FileCheck %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx,+fma4,+xop | FileCheck %s
 
 define <2 x double> @test_int_x86_xop_vpermil2pd(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2) {
-  ; CHECK: vpermil2pd
+; CHECK-LABEL: test_int_x86_xop_vpermil2pd:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpermil2pd $1, %xmm2, %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retq
   %res = call <2 x double> @llvm.x86.xop.vpermil2pd(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2, i8 1) ;  [#uses=1]
   ret <2 x double> %res
 }
 define <2 x double> @test_int_x86_xop_vpermil2pd_mr(<2 x double> %a0, <2 x double>* %a1, <2 x double> %a2) {
-  ; CHECK-NOT: vmovaps
-  ; CHECK: vpermil2pd
+; CHECK-LABEL: test_int_x86_xop_vpermil2pd_mr:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpermil2pd $1, %xmm1, (%rdi), %xmm0, %xmm0
+; CHECK-NEXT:    retq
   %vec = load <2 x double>, <2 x double>* %a1
   %res = call <2 x double> @llvm.x86.xop.vpermil2pd(<2 x double> %a0, <2 x double> %vec, <2 x double> %a2, i8 1) ;  [#uses=1]
   ret <2 x double> %res
 }
 define <2 x double> @test_int_x86_xop_vpermil2pd_rm(<2 x double> %a0, <2 x double> %a1, <2 x double>* %a2) {
-  ; CHECK-NOT: vmovaps
-  ; CHECK: vpermil2pd
+; CHECK-LABEL: test_int_x86_xop_vpermil2pd_rm:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpermil2pd $1, (%rdi), %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retq
   %vec = load <2 x double>, <2 x double>* %a2
   %res = call <2 x double> @llvm.x86.xop.vpermil2pd(<2 x double> %a0, <2 x double> %a1, <2 x double> %vec, i8 1) ;  [#uses=1]
   ret <2 x double> %res
@@ -22,23 +30,27 @@ define <2 x double> @test_int_x86_xop_vpermil2pd_rm(<2 x double> %a0, <2 x doubl
 declare <2 x double> @llvm.x86.xop.vpermil2pd(<2 x double>, <2 x double>, <2 x double>, i8) nounwind readnone
 
 define <4 x double> @test_int_x86_xop_vpermil2pd_256(<4 x double> %a0, <4 x double> %a1, <4 x double> %a2) {
-  ; CHECK: vpermil2pd
-  ; CHECK: ymm
+; CHECK-LABEL: test_int_x86_xop_vpermil2pd_256:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpermil2pd $2, %ymm2, %ymm1, %ymm0, %ymm0
+; CHECK-NEXT:    retq
   %res = call <4 x double> @llvm.x86.xop.vpermil2pd.256(<4 x double> %a0, <4 x double> %a1, <4 x double> %a2, i8 2) ;
   ret <4 x double> %res
 }
 define <4 x double> @test_int_x86_xop_vpermil2pd_256_mr(<4 x double> %a0, <4 x double>* %a1, <4 x double> %a2) {
-  ; CHECK-NOT: vmovaps
-  ; CHECK: vpermil2pd
-  ; CHECK: ymm
+; CHECK-LABEL: test_int_x86_xop_vpermil2pd_256_mr:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpermil2pd $2, %ymm1, (%rdi), %ymm0, %ymm0
+; CHECK-NEXT:    retq
   %vec = load <4 x double>, <4 x double>* %a1
   %res = call <4 x double> @llvm.x86.xop.vpermil2pd.256(<4 x double> %a0, <4 x double> %vec, <4 x double> %a2, i8 2) ;
   ret <4 x double> %res
 }
 define <4 x double> @test_int_x86_xop_vpermil2pd_256_rm(<4 x double> %a0, <4 x double> %a1, <4 x double>* %a2) {
-  ; CHECK-NOT: vmovaps
-  ; CHECK: vpermil2pd
-  ; CHECK: ymm
+; CHECK-LABEL: test_int_x86_xop_vpermil2pd_256_rm:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpermil2pd $2, (%rdi), %ymm1, %ymm0, %ymm0
+; CHECK-NEXT:    retq
   %vec = load <4 x double>, <4 x double>* %a2
   %res = call <4 x double> @llvm.x86.xop.vpermil2pd.256(<4 x double> %a0, <4 x double> %a1, <4 x double> %vec, i8 2) ;
   ret <4 x double> %res
@@ -46,44 +58,57 @@ define <4 x double> @test_int_x86_xop_vpermil2pd_256_rm(<4 x double> %a0, <4 x d
 declare <4 x double> @llvm.x86.xop.vpermil2pd.256(<4 x double>, <4 x double>, <4 x double>, i8) nounwind readnone
 
 define <4 x float> @test_int_x86_xop_vpermil2ps(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2) {
-  ; CHECK: vpermil2ps
+; CHECK-LABEL: test_int_x86_xop_vpermil2ps:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpermil2ps $3, %xmm2, %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retq
   %res = call <4 x float> @llvm.x86.xop.vpermil2ps(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2, i8 3) ;
   ret <4 x float> %res
 }
 declare <4 x float> @llvm.x86.xop.vpermil2ps(<4 x float>, <4 x float>, <4 x float>, i8) nounwind readnone
 
 define <8 x float> @test_int_x86_xop_vpermil2ps_256(<8 x float> %a0, <8 x float> %a1, <8 x float> %a2) {
-  ; CHECK: vpermil2ps
-  ; CHECK: ymm
+; CHECK-LABEL: test_int_x86_xop_vpermil2ps_256:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpermil2ps $4, %ymm2, %ymm1, %ymm0, %ymm0
+; CHECK-NEXT:    retq
   %res = call <8 x float> @llvm.x86.xop.vpermil2ps.256(<8 x float> %a0, <8 x float> %a1, <8 x float> %a2, i8 4) ;
   ret <8 x float> %res
 }
 declare <8 x float> @llvm.x86.xop.vpermil2ps.256(<8 x float>, <8 x float>, <8 x float>, i8) nounwind readnone
 
 define <2 x i64> @test_int_x86_xop_vpcmov(<2 x i64> %a0, <2 x i64> %a1, <2 x i64> %a2) {
-  ; CHECK: vpcmov %xmm2, %xmm1, %xmm0, %xmm0
+; CHECK-LABEL: test_int_x86_xop_vpcmov:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpcmov %xmm2, %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retq
   %res = call <2 x i64> @llvm.x86.xop.vpcmov(<2 x i64> %a0, <2 x i64> %a1, <2 x i64> %a2) ;
   ret <2 x i64> %res
 }
 declare <2 x i64> @llvm.x86.xop.vpcmov(<2 x i64>, <2 x i64>, <2 x i64>) nounwind readnone
 
 define <4 x i64> @test_int_x86_xop_vpcmov_256(<4 x i64> %a0, <4 x i64> %a1, <4 x i64> %a2) {
-  ; CHECK: vpcmov %ymm2, %ymm1, %ymm0, %ymm0
+; CHECK-LABEL: test_int_x86_xop_vpcmov_256:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpcmov %ymm2, %ymm1, %ymm0, %ymm0
+; CHECK-NEXT:    retq
   %res = call <4 x i64> @llvm.x86.xop.vpcmov.256(<4 x i64> %a0, <4 x i64> %a1, <4 x i64> %a2) ;
   ret <4 x i64> %res
 }
 define <4 x i64> @test_int_x86_xop_vpcmov_256_mr(<4 x i64> %a0, <4 x i64>* %a1, <4 x i64> %a2) {
-  ; CHECK-NOT: vmovaps
-  ; CHECK: vpcmov
-  ; CHECK: ymm
+; CHECK-LABEL: test_int_x86_xop_vpcmov_256_mr:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpcmov %ymm1, (%rdi), %ymm0, %ymm0
+; CHECK-NEXT:    retq
   %vec = load <4 x i64>, <4 x i64>* %a1
   %res = call <4 x i64> @llvm.x86.xop.vpcmov.256(<4 x i64> %a0, <4 x i64> %vec, <4 x i64> %a2) ;
   ret <4 x i64> %res
 }
 define <4 x i64> @test_int_x86_xop_vpcmov_256_rm(<4 x i64> %a0, <4 x i64> %a1, <4 x i64>* %a2) {
-  ; CHECK-NOT: vmovaps
-  ; CHECK: vpcmov
-  ; CHECK: ymm
+; CHECK-LABEL: test_int_x86_xop_vpcmov_256_rm:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpcmov (%rdi), %ymm1, %ymm0, %ymm0
+; CHECK-NEXT:    retq
  %vec = load <4 x i64>, <4 x i64>* %a2
  %res = call <4 x i64> @llvm.x86.xop.vpcmov.256(<4 x i64> %a0, <4 x i64> %a1, <4 x i64> %vec) ;
   ret <4 x i64> %res
@@ -91,13 +116,18 @@ define <4 x i64> @test_int_x86_xop_vpcmov_256_rm(<4 x i64> %a0, <4 x i64> %a1, <
 declare <4 x i64> @llvm.x86.xop.vpcmov.256(<4 x i64>, <4 x i64>, <4 x i64>) nounwind readnone
 
 define <16 x i8> @test_int_x86_xop_vpcomeqb(<16 x i8> %a0, <16 x i8> %a1) {
-  ; CHECK:vpcomeqb
+; CHECK-LABEL: test_int_x86_xop_vpcomeqb:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpcomeqb %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retq
   %res = call <16 x i8> @llvm.x86.xop.vpcomeqb(<16 x i8> %a0, <16 x i8> %a1) ;
   ret <16 x i8> %res
 }
 define <16 x i8> @test_int_x86_xop_vpcomeqb_mem(<16 x i8> %a0, <16 x i8>* %a1) {
-  ; CHECK-NOT: vmovaps
-  ; CHECK:vpcomeqb
+; CHECK-LABEL: test_int_x86_xop_vpcomeqb_mem:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpcomeqb (%rdi), %xmm0, %xmm0
+; CHECK-NEXT:    retq
   %vec = load <16 x i8>, <16 x i8>* %a1
   %res = call <16 x i8> @llvm.x86.xop.vpcomeqb(<16 x i8> %a0, <16 x i8> %vec) ;
   ret <16 x i8> %res
@@ -105,545 +135,778 @@ define <16 x i8> @test_int_x86_xop_vpcomeqb_mem(<16 x i8> %a0, <16 x i8>* %a1) {
 declare <16 x i8> @llvm.x86.xop.vpcomeqb(<16 x i8>, <16 x i8>) nounwind readnone
 
 define <8 x i16> @test_int_x86_xop_vpcomeqw(<8 x i16> %a0, <8 x i16> %a1) {
-  ; CHECK: vpcomeqw
+; CHECK-LABEL: test_int_x86_xop_vpcomeqw:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpcomeqw %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retq
   %res = call <8 x i16> @llvm.x86.xop.vpcomeqw(<8 x i16> %a0, <8 x i16> %a1) ;
   ret <8 x i16> %res
 }
 declare <8 x i16> @llvm.x86.xop.vpcomeqw(<8 x i16>, <8 x i16>) nounwind readnone
 
 define <4 x i32> @test_int_x86_xop_vpcomeqd(<4 x i32> %a0, <4 x i32> %a1) {
-  ; CHECK: vpcomeqd
+; CHECK-LABEL: test_int_x86_xop_vpcomeqd:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpcomeqd %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retq
   %res = call <4 x i32> @llvm.x86.xop.vpcomeqd(<4 x i32> %a0, <4 x i32> %a1) ;
   ret <4 x i32> %res
 }
 declare <4 x i32> @llvm.x86.xop.vpcomeqd(<4 x i32>, <4 x i32>) nounwind readnone
 
 define <2 x i64> @test_int_x86_xop_vpcomeqq(<2 x i64> %a0, <2 x i64> %a1) {
-  ; CHECK: vpcomeqq
+; CHECK-LABEL: test_int_x86_xop_vpcomeqq:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpcomeqq %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retq
   %res = call <2 x i64> @llvm.x86.xop.vpcomeqq(<2 x i64> %a0, <2 x i64> %a1) ;
   ret <2 x i64> %res
 }
 declare <2 x i64> @llvm.x86.xop.vpcomeqq(<2 x i64>, <2 x i64>) nounwind readnone
 
 define <16 x i8> @test_int_x86_xop_vpcomequb(<16 x i8> %a0, <16 x i8> %a1) {
-  ; CHECK: vpcomequb
+; CHECK-LABEL: test_int_x86_xop_vpcomequb:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpcomequb %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retq
   %res = call <16 x i8> @llvm.x86.xop.vpcomequb(<16 x i8> %a0, <16 x i8> %a1) ;
   ret <16 x i8> %res
 }
 declare <16 x i8> @llvm.x86.xop.vpcomequb(<16 x i8>, <16 x i8>) nounwind readnone
 
 define <4 x i32> @test_int_x86_xop_vpcomequd(<4 x i32> %a0, <4 x i32> %a1) {
-  ; CHECK: vpcomequd
+; CHECK-LABEL: test_int_x86_xop_vpcomequd:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpcomequd %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retq
   %res = call <4 x i32> @llvm.x86.xop.vpcomequd(<4 x i32> %a0, <4 x i32> %a1) ;
   ret <4 x i32> %res
 }
 declare <4 x i32> @llvm.x86.xop.vpcomequd(<4 x i32>, <4 x i32>) nounwind readnone
 
 define <2 x i64> @test_int_x86_xop_vpcomequq(<2 x i64> %a0, <2 x i64> %a1) {
-  ; CHECK: vpcomequq
+; CHECK-LABEL: test_int_x86_xop_vpcomequq:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpcomequq %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retq
   %res = call <2 x i64> @llvm.x86.xop.vpcomequq(<2 x i64> %a0, <2 x i64> %a1) ;
   ret <2 x i64> %res
 }
 declare <2 x i64> @llvm.x86.xop.vpcomequq(<2 x i64>, <2 x i64>) nounwind readnone
 
 define <8 x i16> @test_int_x86_xop_vpcomequw(<8 x i16> %a0, <8 x i16> %a1) {
-  ; CHECK: vpcomequw
+; CHECK-LABEL: test_int_x86_xop_vpcomequw:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpcomequw %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retq
   %res = call <8 x i16> @llvm.x86.xop.vpcomequw(<8 x i16> %a0, <8 x i16> %a1) ;
   ret <8 x i16> %res
 }
 declare <8 x i16> @llvm.x86.xop.vpcomequw(<8 x i16>, <8 x i16>) nounwind readnone
 
 define <16 x i8> @test_int_x86_xop_vpcomfalseb(<16 x i8> %a0, <16 x i8> %a1) {
-  ; CHECK: vpcomfalseb
+; CHECK-LABEL: test_int_x86_xop_vpcomfalseb:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpcomfalseb %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retq
   %res = call <16 x i8> @llvm.x86.xop.vpcomfalseb(<16 x i8> %a0, <16 x i8> %a1) ;
   ret <16 x i8> %res
 }
 declare <16 x i8> @llvm.x86.xop.vpcomfalseb(<16 x i8>, <16 x i8>) nounwind readnone
 
 define <4 x i32> @test_int_x86_xop_vpcomfalsed(<4 x i32> %a0, <4 x i32> %a1) {
-  ; CHECK: vpcomfalsed
+; CHECK-LABEL: test_int_x86_xop_vpcomfalsed:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpcomfalsed %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retq
   %res = call <4 x i32> @llvm.x86.xop.vpcomfalsed(<4 x i32> %a0, <4 x i32> %a1) ;
   ret <4 x i32> %res
 }
 declare <4 x i32> @llvm.x86.xop.vpcomfalsed(<4 x i32>, <4 x i32>) nounwind readnone
 
 define <2 x i64> @test_int_x86_xop_vpcomfalseq(<2 x i64> %a0, <2 x i64> %a1) {
-  ; CHECK: vpcomfalseq
+; CHECK-LABEL: test_int_x86_xop_vpcomfalseq:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpcomfalseq %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retq
   %res = call <2 x i64> @llvm.x86.xop.vpcomfalseq(<2 x i64> %a0, <2 x i64> %a1) ;
   ret <2 x i64> %res
 }
 declare <2 x i64> @llvm.x86.xop.vpcomfalseq(<2 x i64>, <2 x i64>) nounwind readnone
 
 define <16 x i8> @test_int_x86_xop_vpcomfalseub(<16 x i8> %a0, <16 x i8> %a1) {
-  ; CHECK: vpcomfalseub
+; CHECK-LABEL: test_int_x86_xop_vpcomfalseub:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpcomfalseub %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retq
   %res = call <16 x i8> @llvm.x86.xop.vpcomfalseub(<16 x i8> %a0, <16 x i8> %a1) ;
   ret <16 x i8> %res
 }
 declare <16 x i8> @llvm.x86.xop.vpcomfalseub(<16 x i8>, <16 x i8>) nounwind readnone
 
 define <4 x i32> @test_int_x86_xop_vpcomfalseud(<4 x i32> %a0, <4 x i32> %a1) {
-  ; CHECK: vpcomfalseud
+; CHECK-LABEL: test_int_x86_xop_vpcomfalseud:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpcomfalseud %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retq
   %res = call <4 x i32> @llvm.x86.xop.vpcomfalseud(<4 x i32> %a0, <4 x i32> %a1) ;
   ret <4 x i32> %res
 }
 declare <4 x i32> @llvm.x86.xop.vpcomfalseud(<4 x i32>, <4 x i32>) nounwind readnone
 
 define <2 x i64> @test_int_x86_xop_vpcomfalseuq(<2 x i64> %a0, <2 x i64> %a1) {
-  ; CHECK: vpcomfalseuq
+; CHECK-LABEL: test_int_x86_xop_vpcomfalseuq:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpcomfalseuq %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retq
   %res = call <2 x i64> @llvm.x86.xop.vpcomfalseuq(<2 x i64> %a0, <2 x i64> %a1) ;
   ret <2 x i64> %res
 }
 declare <2 x i64> @llvm.x86.xop.vpcomfalseuq(<2 x i64>, <2 x i64>) nounwind readnone
 
 define <8 x i16> @test_int_x86_xop_vpcomfalseuw(<8 x i16> %a0, <8 x i16> %a1) {
-  ; CHECK: vpcomfalseuw
+; CHECK-LABEL: test_int_x86_xop_vpcomfalseuw:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpcomfalseuw %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retq
   %res = call <8 x i16> @llvm.x86.xop.vpcomfalseuw(<8 x i16> %a0, <8 x i16> %a1) ;
   ret <8 x i16> %res
 }
 declare <8 x i16> @llvm.x86.xop.vpcomfalseuw(<8 x i16>, <8 x i16>) nounwind readnone
 
 define <8 x i16> @test_int_x86_xop_vpcomfalsew(<8 x i16> %a0, <8 x i16> %a1) {
-  ; CHECK: vpcomfalsew
+; CHECK-LABEL: test_int_x86_xop_vpcomfalsew:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpcomfalsew %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retq
   %res = call <8 x i16> @llvm.x86.xop.vpcomfalsew(<8 x i16> %a0, <8 x i16> %a1) ;
   ret <8 x i16> %res
 }
 declare <8 x i16> @llvm.x86.xop.vpcomfalsew(<8 x i16>, <8 x i16>) nounwind readnone
 
 define <16 x i8> @test_int_x86_xop_vpcomgeb(<16 x i8> %a0, <16 x i8> %a1) {
-  ; CHECK: vpcomgeb
+; CHECK-LABEL: test_int_x86_xop_vpcomgeb:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpcomgeb %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retq
   %res = call <16 x i8> @llvm.x86.xop.vpcomgeb(<16 x i8> %a0, <16 x i8> %a1) ;
   ret <16 x i8> %res
 }
 declare <16 x i8> @llvm.x86.xop.vpcomgeb(<16 x i8>, <16 x i8>) nounwind readnone
 
 define <4 x i32> @test_int_x86_xop_vpcomged(<4 x i32> %a0, <4 x i32> %a1) {
-  ; CHECK: vpcomged
+; CHECK-LABEL: test_int_x86_xop_vpcomged:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpcomged %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retq
   %res = call <4 x i32> @llvm.x86.xop.vpcomged(<4 x i32> %a0, <4 x i32> %a1) ;
   ret <4 x i32> %res
 }
 declare <4 x i32> @llvm.x86.xop.vpcomged(<4 x i32>, <4 x i32>) nounwind readnone
 
 define <2 x i64> @test_int_x86_xop_vpcomgeq(<2 x i64> %a0, <2 x i64> %a1) {
-  ; CHECK: vpcomgeq
+; CHECK-LABEL: test_int_x86_xop_vpcomgeq:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpcomgeq %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retq
   %res = call <2 x i64> @llvm.x86.xop.vpcomgeq(<2 x i64> %a0, <2 x i64> %a1) ;
   ret <2 x i64> %res
 }
 declare <2 x i64> @llvm.x86.xop.vpcomgeq(<2 x i64>, <2 x i64>) nounwind readnone
 
 define <16 x i8> @test_int_x86_xop_vpcomgeub(<16 x i8> %a0, <16 x i8> %a1) {
-  ; CHECK: vpcomgeub
+; CHECK-LABEL: test_int_x86_xop_vpcomgeub:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpcomgeub %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retq
   %res = call <16 x i8> @llvm.x86.xop.vpcomgeub(<16 x i8> %a0, <16 x i8> %a1) ;
   ret <16 x i8> %res
 }
 declare <16 x i8> @llvm.x86.xop.vpcomgeub(<16 x i8>, <16 x i8>) nounwind readnone
 
 define <4 x i32> @test_int_x86_xop_vpcomgeud(<4 x i32> %a0, <4 x i32> %a1) {
-  ; CHECK: vpcomgeud
+; CHECK-LABEL: test_int_x86_xop_vpcomgeud:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpcomgeud %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retq
   %res = call <4 x i32> @llvm.x86.xop.vpcomgeud(<4 x i32> %a0, <4 x i32> %a1) ;
   ret <4 x i32> %res
 }
 declare <4 x i32> @llvm.x86.xop.vpcomgeud(<4 x i32>, <4 x i32>) nounwind readnone
 
 define <2 x i64> @test_int_x86_xop_vpcomgeuq(<2 x i64> %a0, <2 x i64> %a1) {
-  ; CHECK: vpcomgeuq
+; CHECK-LABEL: test_int_x86_xop_vpcomgeuq:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpcomgeuq %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retq
   %res = call <2 x i64> @llvm.x86.xop.vpcomgeuq(<2 x i64> %a0, <2 x i64> %a1) ;
   ret <2 x i64> %res
 }
 declare <2 x i64> @llvm.x86.xop.vpcomgeuq(<2 x i64>, <2 x i64>) nounwind readnone
 
 define <8 x i16> @test_int_x86_xop_vpcomgeuw(<8 x i16> %a0, <8 x i16> %a1) {
-  ; CHECK: vpcomgeuw
+; CHECK-LABEL: test_int_x86_xop_vpcomgeuw:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpcomgeuw %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retq
   %res = call <8 x i16> @llvm.x86.xop.vpcomgeuw(<8 x i16> %a0, <8 x i16> %a1) ;
   ret <8 x i16> %res
 }
 declare <8 x i16> @llvm.x86.xop.vpcomgeuw(<8 x i16>, <8 x i16>) nounwind readnone
 
 define <8 x i16> @test_int_x86_xop_vpcomgew(<8 x i16> %a0, <8 x i16> %a1) {
-  ; CHECK: vpcomgew
+; CHECK-LABEL: test_int_x86_xop_vpcomgew:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpcomgew %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retq
   %res = call <8 x i16> @llvm.x86.xop.vpcomgew(<8 x i16> %a0, <8 x i16> %a1) ;
   ret <8 x i16> %res
 }
 declare <8 x i16> @llvm.x86.xop.vpcomgew(<8 x i16>, <8 x i16>) nounwind readnone
 
 define <16 x i8> @test_int_x86_xop_vpcomgtb(<16 x i8> %a0, <16 x i8> %a1) {
-  ; CHECK: vpcomgtb
+; CHECK-LABEL: test_int_x86_xop_vpcomgtb:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpcomgtb %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retq
   %res = call <16 x i8> @llvm.x86.xop.vpcomgtb(<16 x i8> %a0, <16 x i8> %a1) ;
   ret <16 x i8> %res
 }
 declare <16 x i8> @llvm.x86.xop.vpcomgtb(<16 x i8>, <16 x i8>) nounwind readnone
 
 define <4 x i32> @test_int_x86_xop_vpcomgtd(<4 x i32> %a0, <4 x i32> %a1) {
-  ; CHECK: vpcomgtd
+; CHECK-LABEL: test_int_x86_xop_vpcomgtd:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpcomgtd %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retq
   %res = call <4 x i32> @llvm.x86.xop.vpcomgtd(<4 x i32> %a0, <4 x i32> %a1) ;
   ret <4 x i32> %res
 }
 declare <4 x i32> @llvm.x86.xop.vpcomgtd(<4 x i32>, <4 x i32>) nounwind readnone
 
 define <2 x i64> @test_int_x86_xop_vpcomgtq(<2 x i64> %a0, <2 x i64> %a1) {
-  ; CHECK: vpcomgtq
+; CHECK-LABEL: test_int_x86_xop_vpcomgtq:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpcomgtq %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retq
   %res = call <2 x i64> @llvm.x86.xop.vpcomgtq(<2 x i64> %a0, <2 x i64> %a1) ;
   ret <2 x i64> %res
 }
 declare <2 x i64> @llvm.x86.xop.vpcomgtq(<2 x i64>, <2 x i64>) nounwind readnone
 
 define <16 x i8> @test_int_x86_xop_vpcomgtub(<16 x i8> %a0, <16 x i8> %a1) {
-  ; CHECK: vpcomgtub
+; CHECK-LABEL: test_int_x86_xop_vpcomgtub:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpcomgtub %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retq
   %res = call <16 x i8> @llvm.x86.xop.vpcomgtub(<16 x i8> %a0, <16 x i8> %a1) ;
   ret <16 x i8> %res
 }
 declare <16 x i8> @llvm.x86.xop.vpcomgtub(<16 x i8>, <16 x i8>) nounwind readnone
 
 define <4 x i32> @test_int_x86_xop_vpcomgtud(<4 x i32> %a0, <4 x i32> %a1) {
-  ; CHECK: vpcomgtud
+; CHECK-LABEL: test_int_x86_xop_vpcomgtud:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpcomgtud %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retq
   %res = call <4 x i32> @llvm.x86.xop.vpcomgtud(<4 x i32> %a0, <4 x i32> %a1) ;
   ret <4 x i32> %res
 }
 declare <4 x i32> @llvm.x86.xop.vpcomgtud(<4 x i32>, <4 x i32>) nounwind readnone
 
 define <2 x i64> @test_int_x86_xop_vpcomgtuq(<2 x i64> %a0, <2 x i64> %a1) {
-  ; CHECK: vpcomgtuq
+; CHECK-LABEL: test_int_x86_xop_vpcomgtuq:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpcomgtuq %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retq
   %res = call <2 x i64> @llvm.x86.xop.vpcomgtuq(<2 x i64> %a0, <2 x i64> %a1) ;
   ret <2 x i64> %res
 }
 declare <2 x i64> @llvm.x86.xop.vpcomgtuq(<2 x i64>, <2 x i64>) nounwind readnone
 
 define <8 x i16> @test_int_x86_xop_vpcomgtuw(<8 x i16> %a0, <8 x i16> %a1) {
-  ; CHECK: vpcomgtuw
+; CHECK-LABEL: test_int_x86_xop_vpcomgtuw:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpcomgtuw %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retq
   %res = call <8 x i16> @llvm.x86.xop.vpcomgtuw(<8 x i16> %a0, <8 x i16> %a1) ;
   ret <8 x i16> %res
 }
 declare <8 x i16> @llvm.x86.xop.vpcomgtuw(<8 x i16>, <8 x i16>) nounwind readnone
 
 define <8 x i16> @test_int_x86_xop_vpcomgtw(<8 x i16> %a0, <8 x i16> %a1) {
-  ; CHECK: vpcomgtw
+; CHECK-LABEL: test_int_x86_xop_vpcomgtw:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpcomgtw %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retq
   %res = call <8 x i16> @llvm.x86.xop.vpcomgtw(<8 x i16> %a0, <8 x i16> %a1) ;
   ret <8 x i16> %res
 }
 declare <8 x i16> @llvm.x86.xop.vpcomgtw(<8 x i16>, <8 x i16>) nounwind readnone
 
 define <16 x i8> @test_int_x86_xop_vpcomleb(<16 x i8> %a0, <16 x i8> %a1) {
-  ; CHECK: vpcomleb
+; CHECK-LABEL: test_int_x86_xop_vpcomleb:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpcomleb %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retq
   %res = call <16 x i8> @llvm.x86.xop.vpcomleb(<16 x i8> %a0, <16 x i8> %a1) ;
   ret <16 x i8> %res
 }
 declare <16 x i8> @llvm.x86.xop.vpcomleb(<16 x i8>, <16 x i8>) nounwind readnone
 
 define <4 x i32> @test_int_x86_xop_vpcomled(<4 x i32> %a0, <4 x i32> %a1) {
-  ; CHECK: vpcomled
+; CHECK-LABEL: test_int_x86_xop_vpcomled:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpcomled %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retq
   %res = call <4 x i32> @llvm.x86.xop.vpcomled(<4 x i32> %a0, <4 x i32> %a1) ;
   ret <4 x i32> %res
 }
 declare <4 x i32> @llvm.x86.xop.vpcomled(<4 x i32>, <4 x i32>) nounwind readnone
 
 define <2 x i64> @test_int_x86_xop_vpcomleq(<2 x i64> %a0, <2 x i64> %a1) {
-  ; CHECK: vpcomleq
+; CHECK-LABEL: test_int_x86_xop_vpcomleq:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpcomleq %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retq
   %res = call <2 x i64> @llvm.x86.xop.vpcomleq(<2 x i64> %a0, <2 x i64> %a1) ;
   ret <2 x i64> %res
 }
 declare <2 x i64> @llvm.x86.xop.vpcomleq(<2 x i64>, <2 x i64>) nounwind readnone
 
 define <16 x i8> @test_int_x86_xop_vpcomleub(<16 x i8> %a0, <16 x i8> %a1) {
-  ; CHECK: vpcomleub
+; CHECK-LABEL: test_int_x86_xop_vpcomleub:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpcomleub %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retq
   %res = call <16 x i8> @llvm.x86.xop.vpcomleub(<16 x i8> %a0, <16 x i8> %a1) ;
   ret <16 x i8> %res
 }
 declare <16 x i8> @llvm.x86.xop.vpcomleub(<16 x i8>, <16 x i8>) nounwind readnone
 
 define <4 x i32> @test_int_x86_xop_vpcomleud(<4 x i32> %a0, <4 x i32> %a1) {
-  ; CHECK: vpcomleud
+; CHECK-LABEL: test_int_x86_xop_vpcomleud:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpcomleud %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retq
   %res = call <4 x i32> @llvm.x86.xop.vpcomleud(<4 x i32> %a0, <4 x i32> %a1) ;
   ret <4 x i32> %res
 }
 declare <4 x i32> @llvm.x86.xop.vpcomleud(<4 x i32>, <4 x i32>) nounwind readnone
 
 define <2 x i64> @test_int_x86_xop_vpcomleuq(<2 x i64> %a0, <2 x i64> %a1) {
-  ; CHECK: vpcomleuq
+; CHECK-LABEL: test_int_x86_xop_vpcomleuq:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpcomleuq %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retq
   %res = call <2 x i64> @llvm.x86.xop.vpcomleuq(<2 x i64> %a0, <2 x i64> %a1) ;
   ret <2 x i64> %res
 }
 declare <2 x i64> @llvm.x86.xop.vpcomleuq(<2 x i64>, <2 x i64>) nounwind readnone
 
 define <8 x i16> @test_int_x86_xop_vpcomleuw(<8 x i16> %a0, <8 x i16> %a1) {
-  ; CHECK: vpcomleuw
+; CHECK-LABEL: test_int_x86_xop_vpcomleuw:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpcomleuw %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retq
   %res = call <8 x i16> @llvm.x86.xop.vpcomleuw(<8 x i16> %a0, <8 x i16> %a1) ;
   ret <8 x i16> %res
 }
 declare <8 x i16> @llvm.x86.xop.vpcomleuw(<8 x i16>, <8 x i16>) nounwind readnone
 
 define <8 x i16> @test_int_x86_xop_vpcomlew(<8 x i16> %a0, <8 x i16> %a1) {
-  ; CHECK: vpcomlew
+; CHECK-LABEL: test_int_x86_xop_vpcomlew:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpcomlew %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retq
   %res = call <8 x i16> @llvm.x86.xop.vpcomlew(<8 x i16> %a0, <8 x i16> %a1) ;
   ret <8 x i16> %res
 }
 declare <8 x i16> @llvm.x86.xop.vpcomlew(<8 x i16>, <8 x i16>) nounwind readnone
 
 define <16 x i8> @test_int_x86_xop_vpcomltb(<16 x i8> %a0, <16 x i8> %a1) {
-  ; CHECK: vpcomltb
+; CHECK-LABEL: test_int_x86_xop_vpcomltb:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpcomltb %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retq
   %res = call <16 x i8> @llvm.x86.xop.vpcomltb(<16 x i8> %a0, <16 x i8> %a1) ;
   ret <16 x i8> %res
 }
 declare <16 x i8> @llvm.x86.xop.vpcomltb(<16 x i8>, <16 x i8>) nounwind readnone
 
 define <4 x i32> @test_int_x86_xop_vpcomltd(<4 x i32> %a0, <4 x i32> %a1) {
-  ; CHECK: vpcomltd
+; CHECK-LABEL: test_int_x86_xop_vpcomltd:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpcomltd %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retq
   %res = call <4 x i32> @llvm.x86.xop.vpcomltd(<4 x i32> %a0, <4 x i32> %a1) ;
   ret <4 x i32> %res
 }
 declare <4 x i32> @llvm.x86.xop.vpcomltd(<4 x i32>, <4 x i32>) nounwind readnone
 
 define <2 x i64> @test_int_x86_xop_vpcomltq(<2 x i64> %a0, <2 x i64> %a1) {
-  ; CHECK: vpcomltq
+; CHECK-LABEL: test_int_x86_xop_vpcomltq:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpcomltq %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retq
   %res = call <2 x i64> @llvm.x86.xop.vpcomltq(<2 x i64> %a0, <2 x i64> %a1) ;
   ret <2 x i64> %res
 }
 declare <2 x i64> @llvm.x86.xop.vpcomltq(<2 x i64>, <2 x i64>) nounwind readnone
 
 define <16 x i8> @test_int_x86_xop_vpcomltub(<16 x i8> %a0, <16 x i8> %a1) {
-  ; CHECK: vpcomltub
+; CHECK-LABEL: test_int_x86_xop_vpcomltub:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpcomltub %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retq
   %res = call <16 x i8> @llvm.x86.xop.vpcomltub(<16 x i8> %a0, <16 x i8> %a1) ;
   ret <16 x i8> %res
 }
 declare <16 x i8> @llvm.x86.xop.vpcomltub(<16 x i8>, <16 x i8>) nounwind readnone
 
 define <4 x i32> @test_int_x86_xop_vpcomltud(<4 x i32> %a0, <4 x i32> %a1) {
-  ; CHECK: vpcomltud
+; CHECK-LABEL: test_int_x86_xop_vpcomltud:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpcomltud %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retq
   %res = call <4 x i32> @llvm.x86.xop.vpcomltud(<4 x i32> %a0, <4 x i32> %a1) ;
   ret <4 x i32> %res
 }
 declare <4 x i32> @llvm.x86.xop.vpcomltud(<4 x i32>, <4 x i32>) nounwind readnone
 
 define <2 x i64> @test_int_x86_xop_vpcomltuq(<2 x i64> %a0, <2 x i64> %a1) {
-  ; CHECK: vpcomltuq
+; CHECK-LABEL: test_int_x86_xop_vpcomltuq:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpcomltuq %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retq
   %res = call <2 x i64> @llvm.x86.xop.vpcomltuq(<2 x i64> %a0, <2 x i64> %a1) ;
   ret <2 x i64> %res
 }
 declare <2 x i64> @llvm.x86.xop.vpcomltuq(<2 x i64>, <2 x i64>) nounwind readnone
 
 define <8 x i16> @test_int_x86_xop_vpcomltuw(<8 x i16> %a0, <8 x i16> %a1) {
-  ; CHECK: vpcomltuw
+; CHECK-LABEL: test_int_x86_xop_vpcomltuw:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpcomltuw %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retq
   %res = call <8 x i16> @llvm.x86.xop.vpcomltuw(<8 x i16> %a0, <8 x i16> %a1) ;
   ret <8 x i16> %res
 }
 declare <8 x i16> @llvm.x86.xop.vpcomltuw(<8 x i16>, <8 x i16>) nounwind readnone
 
 define <8 x i16> @test_int_x86_xop_vpcomltw(<8 x i16> %a0, <8 x i16> %a1) {
-  ; CHECK: vpcomltw
+; CHECK-LABEL: test_int_x86_xop_vpcomltw:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpcomltw %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retq
   %res = call <8 x i16> @llvm.x86.xop.vpcomltw(<8 x i16> %a0, <8 x i16> %a1) ;
   ret <8 x i16> %res
 }
 declare <8 x i16> @llvm.x86.xop.vpcomltw(<8 x i16>, <8 x i16>) nounwind readnone
 
 define <16 x i8> @test_int_x86_xop_vpcomneb(<16 x i8> %a0, <16 x i8> %a1) {
-  ; CHECK: vpcomneqb
+; CHECK-LABEL: test_int_x86_xop_vpcomneb:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpcomneqb %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retq
   %res = call <16 x i8> @llvm.x86.xop.vpcomneb(<16 x i8> %a0, <16 x i8> %a1) ;
   ret <16 x i8> %res
 }
 declare <16 x i8> @llvm.x86.xop.vpcomneb(<16 x i8>, <16 x i8>) nounwind readnone
 
 define <4 x i32> @test_int_x86_xop_vpcomned(<4 x i32> %a0, <4 x i32> %a1) {
-  ; CHECK: vpcomneqd
+; CHECK-LABEL: test_int_x86_xop_vpcomned:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpcomneqd %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retq
   %res = call <4 x i32> @llvm.x86.xop.vpcomned(<4 x i32> %a0, <4 x i32> %a1) ;
   ret <4 x i32> %res
 }
 declare <4 x i32> @llvm.x86.xop.vpcomned(<4 x i32>, <4 x i32>) nounwind readnone
 
 define <2 x i64> @test_int_x86_xop_vpcomneq(<2 x i64> %a0, <2 x i64> %a1) {
-  ; CHECK: vpcomneqq
+; CHECK-LABEL: test_int_x86_xop_vpcomneq:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpcomneqq %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retq
   %res = call <2 x i64> @llvm.x86.xop.vpcomneq(<2 x i64> %a0, <2 x i64> %a1) ;
   ret <2 x i64> %res
 }
 declare <2 x i64> @llvm.x86.xop.vpcomneq(<2 x i64>, <2 x i64>) nounwind readnone
 
 define <16 x i8> @test_int_x86_xop_vpcomneub(<16 x i8> %a0, <16 x i8> %a1) {
-  ; CHECK: vpcomnequb
+; CHECK-LABEL: test_int_x86_xop_vpcomneub:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpcomnequb %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retq
   %res = call <16 x i8> @llvm.x86.xop.vpcomneub(<16 x i8> %a0, <16 x i8> %a1) ;
   ret <16 x i8> %res
 }
 declare <16 x i8> @llvm.x86.xop.vpcomneub(<16 x i8>, <16 x i8>) nounwind readnone
 
 define <4 x i32> @test_int_x86_xop_vpcomneud(<4 x i32> %a0, <4 x i32> %a1) {
-  ; CHECK: vpcomnequd
+; CHECK-LABEL: test_int_x86_xop_vpcomneud:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpcomnequd %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retq
   %res = call <4 x i32> @llvm.x86.xop.vpcomneud(<4 x i32> %a0, <4 x i32> %a1) ;
   ret <4 x i32> %res
 }
 declare <4 x i32> @llvm.x86.xop.vpcomneud(<4 x i32>, <4 x i32>) nounwind readnone
 
 define <2 x i64> @test_int_x86_xop_vpcomneuq(<2 x i64> %a0, <2 x i64> %a1) {
-  ; CHECK: vpcomnequq
+; CHECK-LABEL: test_int_x86_xop_vpcomneuq:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpcomnequq %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retq
   %res = call <2 x i64> @llvm.x86.xop.vpcomneuq(<2 x i64> %a0, <2 x i64> %a1) ;
   ret <2 x i64> %res
 }
 declare <2 x i64> @llvm.x86.xop.vpcomneuq(<2 x i64>, <2 x i64>) nounwind readnone
 
 define <8 x i16> @test_int_x86_xop_vpcomneuw(<8 x i16> %a0, <8 x i16> %a1) {
-  ; CHECK: vpcomnequw
+; CHECK-LABEL: test_int_x86_xop_vpcomneuw:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpcomnequw %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retq
   %res = call <8 x i16> @llvm.x86.xop.vpcomneuw(<8 x i16> %a0, <8 x i16> %a1) ;
   ret <8 x i16> %res
 }
 declare <8 x i16> @llvm.x86.xop.vpcomneuw(<8 x i16>, <8 x i16>) nounwind readnone
 
 define <8 x i16> @test_int_x86_xop_vpcomnew(<8 x i16> %a0, <8 x i16> %a1) {
-  ; CHECK: vpcomneqw
+; CHECK-LABEL: test_int_x86_xop_vpcomnew:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpcomneqw %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retq
   %res = call <8 x i16> @llvm.x86.xop.vpcomnew(<8 x i16> %a0, <8 x i16> %a1) ;
   ret <8 x i16> %res
 }
 declare <8 x i16> @llvm.x86.xop.vpcomnew(<8 x i16>, <8 x i16>) nounwind readnone
 
 define <16 x i8> @test_int_x86_xop_vpcomtrueb(<16 x i8> %a0, <16 x i8> %a1) {
-  ; CHECK: vpcomtrueb
+; CHECK-LABEL: test_int_x86_xop_vpcomtrueb:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpcomtrueb %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retq
   %res = call <16 x i8> @llvm.x86.xop.vpcomtrueb(<16 x i8> %a0, <16 x i8> %a1) ;
   ret <16 x i8> %res
 }
 declare <16 x i8> @llvm.x86.xop.vpcomtrueb(<16 x i8>, <16 x i8>) nounwind readnone
 
 define <4 x i32> @test_int_x86_xop_vpcomtrued(<4 x i32> %a0, <4 x i32> %a1) {
-  ; CHECK: vpcomtrued
+; CHECK-LABEL: test_int_x86_xop_vpcomtrued:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpcomtrued %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retq
   %res = call <4 x i32> @llvm.x86.xop.vpcomtrued(<4 x i32> %a0, <4 x i32> %a1) ;
   ret <4 x i32> %res
 }
 declare <4 x i32> @llvm.x86.xop.vpcomtrued(<4 x i32>, <4 x i32>) nounwind readnone
 
 define <2 x i64> @test_int_x86_xop_vpcomtrueq(<2 x i64> %a0, <2 x i64> %a1) {
-  ; CHECK: vpcomtrueq
+; CHECK-LABEL: test_int_x86_xop_vpcomtrueq:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpcomtrueq %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retq
   %res = call <2 x i64> @llvm.x86.xop.vpcomtrueq(<2 x i64> %a0, <2 x i64> %a1) ;
   ret <2 x i64> %res
 }
 declare <2 x i64> @llvm.x86.xop.vpcomtrueq(<2 x i64>, <2 x i64>) nounwind readnone
 
 define <16 x i8> @test_int_x86_xop_vpcomtrueub(<16 x i8> %a0, <16 x i8> %a1) {
-  ; CHECK: vpcomtrueub
+; CHECK-LABEL: test_int_x86_xop_vpcomtrueub:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpcomtrueub %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retq
   %res = call <16 x i8> @llvm.x86.xop.vpcomtrueub(<16 x i8> %a0, <16 x i8> %a1) ;
   ret <16 x i8> %res
 }
 declare <16 x i8> @llvm.x86.xop.vpcomtrueub(<16 x i8>, <16 x i8>) nounwind readnone
 
 define <4 x i32> @test_int_x86_xop_vpcomtrueud(<4 x i32> %a0, <4 x i32> %a1) {
-  ; CHECK: vpcomtrueud
+; CHECK-LABEL: test_int_x86_xop_vpcomtrueud:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpcomtrueud %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retq
   %res = call <4 x i32> @llvm.x86.xop.vpcomtrueud(<4 x i32> %a0, <4 x i32> %a1) ;
   ret <4 x i32> %res
 }
 declare <4 x i32> @llvm.x86.xop.vpcomtrueud(<4 x i32>, <4 x i32>) nounwind readnone
 
 define <2 x i64> @test_int_x86_xop_vpcomtrueuq(<2 x i64> %a0, <2 x i64> %a1) {
-  ; CHECK: vpcomtrueuq
+; CHECK-LABEL: test_int_x86_xop_vpcomtrueuq:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpcomtrueuq %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retq
   %res = call <2 x i64> @llvm.x86.xop.vpcomtrueuq(<2 x i64> %a0, <2 x i64> %a1) ;
   ret <2 x i64> %res
 }
 declare <2 x i64> @llvm.x86.xop.vpcomtrueuq(<2 x i64>, <2 x i64>) nounwind readnone
 
 define <8 x i16> @test_int_x86_xop_vpcomtrueuw(<8 x i16> %a0, <8 x i16> %a1) {
-  ; CHECK: vpcomtrueuw
+; CHECK-LABEL: test_int_x86_xop_vpcomtrueuw:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpcomtrueuw %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retq
   %res = call <8 x i16> @llvm.x86.xop.vpcomtrueuw(<8 x i16> %a0, <8 x i16> %a1) ;
   ret <8 x i16> %res
 }
 declare <8 x i16> @llvm.x86.xop.vpcomtrueuw(<8 x i16>, <8 x i16>) nounwind readnone
 
 define <8 x i16> @test_int_x86_xop_vpcomtruew(<8 x i16> %a0, <8 x i16> %a1) {
-  ; CHECK: vpcomtruew
+; CHECK-LABEL: test_int_x86_xop_vpcomtruew:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpcomtruew %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retq
   %res = call <8 x i16> @llvm.x86.xop.vpcomtruew(<8 x i16> %a0, <8 x i16> %a1) ;
   ret <8 x i16> %res
 }
 declare <8 x i16> @llvm.x86.xop.vpcomtruew(<8 x i16>, <8 x i16>) nounwind readnone
 
 define <4 x i32> @test_int_x86_xop_vphaddbd(<16 x i8> %a0) {
-  ; CHECK: vphaddbd
+; CHECK-LABEL: test_int_x86_xop_vphaddbd:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vphaddbd %xmm0, %xmm0
+; CHECK-NEXT:    retq
   %res = call <4 x i32> @llvm.x86.xop.vphaddbd(<16 x i8> %a0) ;
   ret <4 x i32> %res
 }
 declare <4 x i32> @llvm.x86.xop.vphaddbd(<16 x i8>) nounwind readnone
 
 define <2 x i64> @test_int_x86_xop_vphaddbq(<16 x i8> %a0) {
-  ; CHECK: vphaddbq
+; CHECK-LABEL: test_int_x86_xop_vphaddbq:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vphaddbq %xmm0, %xmm0
+; CHECK-NEXT:    retq
   %res = call <2 x i64> @llvm.x86.xop.vphaddbq(<16 x i8> %a0) ;
   ret <2 x i64> %res
 }
 declare <2 x i64> @llvm.x86.xop.vphaddbq(<16 x i8>) nounwind readnone
 
 define <8 x i16> @test_int_x86_xop_vphaddbw(<16 x i8> %a0) {
-  ; CHECK: vphaddbw
+; CHECK-LABEL: test_int_x86_xop_vphaddbw:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vphaddbw %xmm0, %xmm0
+; CHECK-NEXT:    retq
   %res = call <8 x i16> @llvm.x86.xop.vphaddbw(<16 x i8> %a0) ;
   ret <8 x i16> %res
 }
 declare <8 x i16> @llvm.x86.xop.vphaddbw(<16 x i8>) nounwind readnone
 
 define <2 x i64> @test_int_x86_xop_vphadddq(<4 x i32> %a0) {
-  ; CHECK: vphadddq
+; CHECK-LABEL: test_int_x86_xop_vphadddq:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vphadddq %xmm0, %xmm0
+; CHECK-NEXT:    retq
   %res = call <2 x i64> @llvm.x86.xop.vphadddq(<4 x i32> %a0) ;
   ret <2 x i64> %res
 }
 declare <2 x i64> @llvm.x86.xop.vphadddq(<4 x i32>) nounwind readnone
 
 define <4 x i32> @test_int_x86_xop_vphaddubd(<16 x i8> %a0) {
-  ; CHECK: vphaddubd
+; CHECK-LABEL: test_int_x86_xop_vphaddubd:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vphaddubd %xmm0, %xmm0
+; CHECK-NEXT:    retq
   %res = call <4 x i32> @llvm.x86.xop.vphaddubd(<16 x i8> %a0) ;
   ret <4 x i32> %res
 }
 declare <4 x i32> @llvm.x86.xop.vphaddubd(<16 x i8>) nounwind readnone
 
 define <2 x i64> @test_int_x86_xop_vphaddubq(<16 x i8> %a0) {
-  ; CHECK: vphaddubq
+; CHECK-LABEL: test_int_x86_xop_vphaddubq:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vphaddubq %xmm0, %xmm0
+; CHECK-NEXT:    retq
   %res = call <2 x i64> @llvm.x86.xop.vphaddubq(<16 x i8> %a0) ;
   ret <2 x i64> %res
 }
 declare <2 x i64> @llvm.x86.xop.vphaddubq(<16 x i8>) nounwind readnone
 
 define <8 x i16> @test_int_x86_xop_vphaddubw(<16 x i8> %a0) {
-  ; CHECK: vphaddubw
+; CHECK-LABEL: test_int_x86_xop_vphaddubw:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vphaddubw %xmm0, %xmm0
+; CHECK-NEXT:    retq
   %res = call <8 x i16> @llvm.x86.xop.vphaddubw(<16 x i8> %a0) ;
   ret <8 x i16> %res
 }
 declare <8 x i16> @llvm.x86.xop.vphaddubw(<16 x i8>) nounwind readnone
 
 define <2 x i64> @test_int_x86_xop_vphaddudq(<4 x i32> %a0) {
-  ; CHECK: vphaddudq
+; CHECK-LABEL: test_int_x86_xop_vphaddudq:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vphaddudq %xmm0, %xmm0
+; CHECK-NEXT:    retq
   %res = call <2 x i64> @llvm.x86.xop.vphaddudq(<4 x i32> %a0) ;
   ret <2 x i64> %res
 }
 declare <2 x i64> @llvm.x86.xop.vphaddudq(<4 x i32>) nounwind readnone
 
 define <4 x i32> @test_int_x86_xop_vphadduwd(<8 x i16> %a0) {
-  ; CHECK: vphadduwd
+; CHECK-LABEL: test_int_x86_xop_vphadduwd:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vphadduwd %xmm0, %xmm0
+; CHECK-NEXT:    retq
   %res = call <4 x i32> @llvm.x86.xop.vphadduwd(<8 x i16> %a0) ;
   ret <4 x i32> %res
 }
 declare <4 x i32> @llvm.x86.xop.vphadduwd(<8 x i16>) nounwind readnone
 
 define <2 x i64> @test_int_x86_xop_vphadduwq(<8 x i16> %a0) {
-  ; CHECK: vphadduwq
+; CHECK-LABEL: test_int_x86_xop_vphadduwq:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vphadduwq %xmm0, %xmm0
+; CHECK-NEXT:    retq
   %res = call <2 x i64> @llvm.x86.xop.vphadduwq(<8 x i16> %a0) ;
   ret <2 x i64> %res
 }
 declare <2 x i64> @llvm.x86.xop.vphadduwq(<8 x i16>) nounwind readnone
 
 define <4 x i32> @test_int_x86_xop_vphaddwd(<8 x i16> %a0) {
-  ; CHECK: vphaddwd
+; CHECK-LABEL: test_int_x86_xop_vphaddwd:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vphaddwd %xmm0, %xmm0
+; CHECK-NEXT:    retq
   %res = call <4 x i32> @llvm.x86.xop.vphaddwd(<8 x i16> %a0) ;
   ret <4 x i32> %res
 }
 declare <4 x i32> @llvm.x86.xop.vphaddwd(<8 x i16>) nounwind readnone
 
 define <2 x i64> @test_int_x86_xop_vphaddwq(<8 x i16> %a0) {
-  ; CHECK: vphaddwq
+; CHECK-LABEL: test_int_x86_xop_vphaddwq:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vphaddwq %xmm0, %xmm0
+; CHECK-NEXT:    retq
   %res = call <2 x i64> @llvm.x86.xop.vphaddwq(<8 x i16> %a0) ;
   ret <2 x i64> %res
 }
 declare <2 x i64> @llvm.x86.xop.vphaddwq(<8 x i16>) nounwind readnone
 
 define <8 x i16> @test_int_x86_xop_vphsubbw(<16 x i8> %a0) {
-  ; CHECK: vphsubbw
+; CHECK-LABEL: test_int_x86_xop_vphsubbw:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vphsubbw %xmm0, %xmm0
+; CHECK-NEXT:    retq
   %res = call <8 x i16> @llvm.x86.xop.vphsubbw(<16 x i8> %a0) ;
   ret <8 x i16> %res
 }
 declare <8 x i16> @llvm.x86.xop.vphsubbw(<16 x i8>) nounwind readnone
 
 define <2 x i64> @test_int_x86_xop_vphsubdq(<4 x i32> %a0) {
-  ; CHECK: vphsubdq
+; CHECK-LABEL: test_int_x86_xop_vphsubdq:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vphsubdq %xmm0, %xmm0
+; CHECK-NEXT:    retq
   %res = call <2 x i64> @llvm.x86.xop.vphsubdq(<4 x i32> %a0) ;
   ret <2 x i64> %res
 }
 define <2 x i64> @test_int_x86_xop_vphsubdq_mem(<4 x i32>* %a0) {
-  ; CHECK-NOT: vmovaps
-  ; CHECK: vphsubdq
+; CHECK-LABEL: test_int_x86_xop_vphsubdq_mem:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vphsubdq (%rdi), %xmm0
+; CHECK-NEXT:    retq
   %vec = load <4 x i32>, <4 x i32>* %a0
   %res = call <2 x i64> @llvm.x86.xop.vphsubdq(<4 x i32> %vec) ;
   ret <2 x i64> %res
@@ -651,13 +914,18 @@ define <2 x i64> @test_int_x86_xop_vphsubdq_mem(<4 x i32>* %a0) {
 declare <2 x i64> @llvm.x86.xop.vphsubdq(<4 x i32>) nounwind readnone
 
 define <4 x i32> @test_int_x86_xop_vphsubwd(<8 x i16> %a0) {
-  ; CHECK: vphsubwd
+; CHECK-LABEL: test_int_x86_xop_vphsubwd:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vphsubwd %xmm0, %xmm0
+; CHECK-NEXT:    retq
   %res = call <4 x i32> @llvm.x86.xop.vphsubwd(<8 x i16> %a0) ;
   ret <4 x i32> %res
 }
 define <4 x i32> @test_int_x86_xop_vphsubwd_mem(<8 x i16>* %a0) {
-  ; CHECK-NOT: vmovaps
-  ; CHECK: vphsubwd
+; CHECK-LABEL: test_int_x86_xop_vphsubwd_mem:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vphsubwd (%rdi), %xmm0
+; CHECK-NEXT:    retq
   %vec = load <8 x i16>, <8 x i16>* %a0
   %res = call <4 x i32> @llvm.x86.xop.vphsubwd(<8 x i16> %vec) ;
   ret <4 x i32> %res
@@ -665,90 +933,128 @@ define <4 x i32> @test_int_x86_xop_vphsubwd_mem(<8 x i16>* %a0) {
 declare <4 x i32> @llvm.x86.xop.vphsubwd(<8 x i16>) nounwind readnone
 
 define <4 x i32> @test_int_x86_xop_vpmacsdd(<4 x i32> %a0, <4 x i32> %a1, <4 x i32> %a2) {
-  ; CHECK: vpmacsdd
+; CHECK-LABEL: test_int_x86_xop_vpmacsdd:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpmacsdd %xmm2, %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retq
   %res = call <4 x i32> @llvm.x86.xop.vpmacsdd(<4 x i32> %a0, <4 x i32> %a1, <4 x i32> %a2) ;
   ret <4 x i32> %res
 }
 declare <4 x i32> @llvm.x86.xop.vpmacsdd(<4 x i32>, <4 x i32>, <4 x i32>) nounwind readnone
 
 define <2 x i64> @test_int_x86_xop_vpmacsdqh(<4 x i32> %a0, <4 x i32> %a1, <2 x i64> %a2) {
-  ; CHECK: vpmacsdqh
+; CHECK-LABEL: test_int_x86_xop_vpmacsdqh:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpmacsdqh %xmm2, %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retq
   %res = call <2 x i64> @llvm.x86.xop.vpmacsdqh(<4 x i32> %a0, <4 x i32> %a1, <2 x i64> %a2) ;
   ret <2 x i64> %res
 }
 declare <2 x i64> @llvm.x86.xop.vpmacsdqh(<4 x i32>, <4 x i32>, <2 x i64>) nounwind readnone
 
 define <2 x i64> @test_int_x86_xop_vpmacsdql(<4 x i32> %a0, <4 x i32> %a1, <2 x i64> %a2) {
-  ; CHECK: vpmacsdql
+; CHECK-LABEL: test_int_x86_xop_vpmacsdql:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpmacsdql %xmm2, %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retq
   %res = call <2 x i64> @llvm.x86.xop.vpmacsdql(<4 x i32> %a0, <4 x i32> %a1, <2 x i64> %a2) ;
   ret <2 x i64> %res
 }
 declare <2 x i64> @llvm.x86.xop.vpmacsdql(<4 x i32>, <4 x i32>, <2 x i64>) nounwind readnone
 
 define <4 x i32> @test_int_x86_xop_vpmacssdd(<4 x i32> %a0, <4 x i32> %a1, <4 x i32> %a2) {
-  ; CHECK: vpmacssdd
+; CHECK-LABEL: test_int_x86_xop_vpmacssdd:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpmacssdd %xmm2, %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retq
   %res = call <4 x i32> @llvm.x86.xop.vpmacssdd(<4 x i32> %a0, <4 x i32> %a1, <4 x i32> %a2) ;
   ret <4 x i32> %res
 }
 declare <4 x i32> @llvm.x86.xop.vpmacssdd(<4 x i32>, <4 x i32>, <4 x i32>) nounwind readnone
 
 define <2 x i64> @test_int_x86_xop_vpmacssdqh(<4 x i32> %a0, <4 x i32> %a1, <2 x i64> %a2) {
-  ; CHECK: vpmacssdqh
+; CHECK-LABEL: test_int_x86_xop_vpmacssdqh:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpmacssdqh %xmm2, %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retq
   %res = call <2 x i64> @llvm.x86.xop.vpmacssdqh(<4 x i32> %a0, <4 x i32> %a1, <2 x i64> %a2) ;
   ret <2 x i64> %res
 }
 declare <2 x i64> @llvm.x86.xop.vpmacssdqh(<4 x i32>, <4 x i32>, <2 x i64>) nounwind readnone
 
 define <2 x i64> @test_int_x86_xop_vpmacssdql(<4 x i32> %a0, <4 x i32> %a1, <2 x i64> %a2) {
-  ; CHECK: vpmacssdql
+; CHECK-LABEL: test_int_x86_xop_vpmacssdql:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpmacssdql %xmm2, %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retq
   %res = call <2 x i64> @llvm.x86.xop.vpmacssdql(<4 x i32> %a0, <4 x i32> %a1, <2 x i64> %a2) ;
   ret <2 x i64> %res
 }
 declare <2 x i64> @llvm.x86.xop.vpmacssdql(<4 x i32>, <4 x i32>, <2 x i64>) nounwind readnone
 
 define <4 x i32> @test_int_x86_xop_vpmacsswd(<8 x i16> %a0, <8 x i16> %a1, <4 x i32> %a2) {
-  ; CHECK: vpmacsswd
+; CHECK-LABEL: test_int_x86_xop_vpmacsswd:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpmacsswd %xmm2, %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retq
   %res = call <4 x i32> @llvm.x86.xop.vpmacsswd(<8 x i16> %a0, <8 x i16> %a1, <4 x i32> %a2) ;
   ret <4 x i32> %res
 }
 declare <4 x i32> @llvm.x86.xop.vpmacsswd(<8 x i16>, <8 x i16>, <4 x i32>) nounwind readnone
 
 define <8 x i16> @test_int_x86_xop_vpmacssww(<8 x i16> %a0, <8 x i16> %a1, <8 x i16> %a2) {
-  ; CHECK: vpmacssww
+; CHECK-LABEL: test_int_x86_xop_vpmacssww:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpmacssww %xmm2, %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retq
   %res = call <8 x i16> @llvm.x86.xop.vpmacssww(<8 x i16> %a0, <8 x i16> %a1, <8 x i16> %a2) ;
   ret <8 x i16> %res
 }
 declare <8 x i16> @llvm.x86.xop.vpmacssww(<8 x i16>, <8 x i16>, <8 x i16>) nounwind readnone
 
 define <4 x i32> @test_int_x86_xop_vpmacswd(<8 x i16> %a0, <8 x i16> %a1, <4 x i32> %a2) {
-  ; CHECK: vpmacswd
+; CHECK-LABEL: test_int_x86_xop_vpmacswd:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpmacswd %xmm2, %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retq
   %res = call <4 x i32> @llvm.x86.xop.vpmacswd(<8 x i16> %a0, <8 x i16> %a1, <4 x i32> %a2) ;
   ret <4 x i32> %res
 }
 declare <4 x i32> @llvm.x86.xop.vpmacswd(<8 x i16>, <8 x i16>, <4 x i32>) nounwind readnone
 
 define <8 x i16> @test_int_x86_xop_vpmacsww(<8 x i16> %a0, <8 x i16> %a1, <8 x i16> %a2) {
-  ; CHECK: vpmacsww
+; CHECK-LABEL: test_int_x86_xop_vpmacsww:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpmacsww %xmm2, %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retq
   %res = call <8 x i16> @llvm.x86.xop.vpmacsww(<8 x i16> %a0, <8 x i16> %a1, <8 x i16> %a2) ;
   ret <8 x i16> %res
 }
 declare <8 x i16> @llvm.x86.xop.vpmacsww(<8 x i16>, <8 x i16>, <8 x i16>) nounwind readnone
 
 define <4 x i32> @test_int_x86_xop_vpmadcsswd(<8 x i16> %a0, <8 x i16> %a1, <4 x i32> %a2) {
-  ; CHECK: vpmadcsswd
+; CHECK-LABEL: test_int_x86_xop_vpmadcsswd:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpmadcsswd %xmm2, %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retq
   %res = call <4 x i32> @llvm.x86.xop.vpmadcsswd(<8 x i16> %a0, <8 x i16> %a1, <4 x i32> %a2) ;
   ret <4 x i32> %res
 }
 declare <4 x i32> @llvm.x86.xop.vpmadcsswd(<8 x i16>, <8 x i16>, <4 x i32>) nounwind readnone
 
 define <4 x i32> @test_int_x86_xop_vpmadcswd(<8 x i16> %a0, <8 x i16> %a1, <4 x i32> %a2) {
-  ; CHECK: vpmadcswd
+; CHECK-LABEL: test_int_x86_xop_vpmadcswd:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpmadcswd %xmm2, %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retq
   %res = call <4 x i32> @llvm.x86.xop.vpmadcswd(<8 x i16> %a0, <8 x i16> %a1, <4 x i32> %a2) ;
   ret <4 x i32> %res
 }
 define <4 x i32> @test_int_x86_xop_vpmadcswd_mem(<8 x i16> %a0, <8 x i16>* %a1, <4 x i32> %a2) {
-  ; CHECK-NOT: vmovaps
-  ; CHECK: vpmadcswd
+; CHECK-LABEL: test_int_x86_xop_vpmadcswd_mem:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpmadcswd %xmm1, (%rdi), %xmm0, %xmm0
+; CHECK-NEXT:    retq
   %vec = load <8 x i16>, <8 x i16>* %a1
   %res = call <4 x i32> @llvm.x86.xop.vpmadcswd(<8 x i16> %a0, <8 x i16> %vec, <4 x i32> %a2) ;
   ret <4 x i32> %res
@@ -756,20 +1062,27 @@ define <4 x i32> @test_int_x86_xop_vpmadcswd_mem(<8 x i16> %a0, <8 x i16>* %a1,
 declare <4 x i32> @llvm.x86.xop.vpmadcswd(<8 x i16>, <8 x i16>, <4 x i32>) nounwind readnone
 
 define <16 x i8> @test_int_x86_xop_vpperm(<16 x i8> %a0, <16 x i8> %a1, <16 x i8> %a2) {
-  ; CHECK: vpperm
+; CHECK-LABEL: test_int_x86_xop_vpperm:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpperm %xmm2, %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retq
   %res = call <16 x i8> @llvm.x86.xop.vpperm(<16 x i8> %a0, <16 x i8> %a1, <16 x i8> %a2) ;
   ret <16 x i8> %res
 }
 define <16 x i8> @test_int_x86_xop_vpperm_rm(<16 x i8> %a0, <16 x i8> %a1, <16 x i8>* %a2) {
-  ; CHECK-NOT: vmovaps
-  ; CHECK: vpperm
+; CHECK-LABEL: test_int_x86_xop_vpperm_rm:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpperm (%rdi), %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retq
   %vec = load <16 x i8>, <16 x i8>* %a2
   %res = call <16 x i8> @llvm.x86.xop.vpperm(<16 x i8> %a0, <16 x i8> %a1, <16 x i8> %vec) ;
   ret <16 x i8> %res
 }
 define <16 x i8> @test_int_x86_xop_vpperm_mr(<16 x i8> %a0, <16 x i8>* %a1, <16 x i8> %a2) {
-  ; CHECK-NOT: vmovaps
-  ; CHECK: vpperm
+; CHECK-LABEL: test_int_x86_xop_vpperm_mr:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpperm %xmm1, (%rdi), %xmm0, %xmm0
+; CHECK-NEXT:    retq
   %vec = load <16 x i8>, <16 x i8>* %a1
   %res = call <16 x i8> @llvm.x86.xop.vpperm(<16 x i8> %a0, <16 x i8> %vec, <16 x i8> %a2) ;
   ret <16 x i8> %res
@@ -777,125 +1090,177 @@ define <16 x i8> @test_int_x86_xop_vpperm_mr(<16 x i8> %a0, <16 x i8>* %a1, <16
 declare <16 x i8> @llvm.x86.xop.vpperm(<16 x i8>, <16 x i8>, <16 x i8>) nounwind readnone
 
 define <16 x i8> @test_int_x86_xop_vprotb(<16 x i8> %a0, <16 x i8> %a1) {
-  ; CHECK: vprotb
+; CHECK-LABEL: test_int_x86_xop_vprotb:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vprotb %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retq
   %res = call <16 x i8> @llvm.x86.xop.vprotb(<16 x i8> %a0, <16 x i8> %a1) ;
   ret <16 x i8> %res
 }
 declare <16 x i8> @llvm.x86.xop.vprotb(<16 x i8>, <16 x i8>) nounwind readnone
 
 define <4 x i32> @test_int_x86_xop_vprotd(<4 x i32> %a0, <4 x i32> %a1) {
-  ; CHECK: vprotd
+; CHECK-LABEL: test_int_x86_xop_vprotd:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vprotd %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retq
   %res = call <4 x i32> @llvm.x86.xop.vprotd(<4 x i32> %a0, <4 x i32> %a1) ;
   ret <4 x i32> %res
 }
 declare <4 x i32> @llvm.x86.xop.vprotd(<4 x i32>, <4 x i32>) nounwind readnone
 
 define <2 x i64> @test_int_x86_xop_vprotq(<2 x i64> %a0, <2 x i64> %a1) {
-  ; CHECK: vprotq
+; CHECK-LABEL: test_int_x86_xop_vprotq:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vprotq %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retq
   %res = call <2 x i64> @llvm.x86.xop.vprotq(<2 x i64> %a0, <2 x i64> %a1) ;
   ret <2 x i64> %res
 }
 declare <2 x i64> @llvm.x86.xop.vprotq(<2 x i64>, <2 x i64>) nounwind readnone
 
 define <8 x i16> @test_int_x86_xop_vprotw(<8 x i16> %a0, <8 x i16> %a1) {
-  ; CHECK: vprotw
+; CHECK-LABEL: test_int_x86_xop_vprotw:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vprotw %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retq
   %res = call <8 x i16> @llvm.x86.xop.vprotw(<8 x i16> %a0, <8 x i16> %a1) ;
   ret <8 x i16> %res
 }
 declare <8 x i16> @llvm.x86.xop.vprotw(<8 x i16>, <8 x i16>) nounwind readnone
 
 define <16 x i8> @test_int_x86_xop_vprotbi(<16 x i8> %a0) {
-  ; CHECK: vprotb
+; CHECK-LABEL: test_int_x86_xop_vprotbi:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vprotb $1, %xmm0, %xmm0
+; CHECK-NEXT:    retq
   %res = call <16 x i8> @llvm.x86.xop.vprotbi(<16 x i8> %a0, i8 1) ;
   ret <16 x i8> %res
 }
 declare <16 x i8> @llvm.x86.xop.vprotbi(<16 x i8>, i8) nounwind readnone
 
 define <4 x i32> @test_int_x86_xop_vprotdi(<4 x i32> %a0) {
-  ; CHECK: vprotd
+; CHECK-LABEL: test_int_x86_xop_vprotdi:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vprotd $254, %xmm0, %xmm0
+; CHECK-NEXT:    retq
   %res = call <4 x i32> @llvm.x86.xop.vprotdi(<4 x i32> %a0, i8 -2) ;
   ret <4 x i32> %res
 }
 declare <4 x i32> @llvm.x86.xop.vprotdi(<4 x i32>, i8) nounwind readnone
 
 define <2 x i64> @test_int_x86_xop_vprotqi(<2 x i64> %a0) {
-  ; CHECK: vprotq
+; CHECK-LABEL: test_int_x86_xop_vprotqi:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vprotq $3, %xmm0, %xmm0
+; CHECK-NEXT:    retq
   %res = call <2 x i64> @llvm.x86.xop.vprotqi(<2 x i64> %a0, i8 3) ;
   ret <2 x i64> %res
 }
 declare <2 x i64> @llvm.x86.xop.vprotqi(<2 x i64>, i8) nounwind readnone
 
 define <8 x i16> @test_int_x86_xop_vprotwi(<8 x i16> %a0) {
-  ; CHECK: vprotw
+; CHECK-LABEL: test_int_x86_xop_vprotwi:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vprotw $252, %xmm0, %xmm0
+; CHECK-NEXT:    retq
   %res = call <8 x i16> @llvm.x86.xop.vprotwi(<8 x i16> %a0, i8 -4) ;
   ret <8 x i16> %res
 }
 declare <8 x i16> @llvm.x86.xop.vprotwi(<8 x i16>, i8) nounwind readnone
 
 define <16 x i8> @test_int_x86_xop_vpshab(<16 x i8> %a0, <16 x i8> %a1) {
-  ; CHECK: vpshab
+; CHECK-LABEL: test_int_x86_xop_vpshab:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpshab %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retq
   %res = call <16 x i8> @llvm.x86.xop.vpshab(<16 x i8> %a0, <16 x i8> %a1) ;
   ret <16 x i8> %res
 }
 declare <16 x i8> @llvm.x86.xop.vpshab(<16 x i8>, <16 x i8>) nounwind readnone
 
 define <4 x i32> @test_int_x86_xop_vpshad(<4 x i32> %a0, <4 x i32> %a1) {
-  ; CHECK: vpshad
+; CHECK-LABEL: test_int_x86_xop_vpshad:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpshad %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retq
   %res = call <4 x i32> @llvm.x86.xop.vpshad(<4 x i32> %a0, <4 x i32> %a1) ;
   ret <4 x i32> %res
 }
 declare <4 x i32> @llvm.x86.xop.vpshad(<4 x i32>, <4 x i32>) nounwind readnone
 
 define <2 x i64> @test_int_x86_xop_vpshaq(<2 x i64> %a0, <2 x i64> %a1) {
-  ; CHECK: vpshaq
+; CHECK-LABEL: test_int_x86_xop_vpshaq:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpshaq %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retq
   %res = call <2 x i64> @llvm.x86.xop.vpshaq(<2 x i64> %a0, <2 x i64> %a1) ;
   ret <2 x i64> %res
 }
 declare <2 x i64> @llvm.x86.xop.vpshaq(<2 x i64>, <2 x i64>) nounwind readnone
 
 define <8 x i16> @test_int_x86_xop_vpshaw(<8 x i16> %a0, <8 x i16> %a1) {
-  ; CHECK: vpshaw
+; CHECK-LABEL: test_int_x86_xop_vpshaw:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpshaw %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retq
   %res = call <8 x i16> @llvm.x86.xop.vpshaw(<8 x i16> %a0, <8 x i16> %a1) ;
   ret <8 x i16> %res
 }
 declare <8 x i16> @llvm.x86.xop.vpshaw(<8 x i16>, <8 x i16>) nounwind readnone
 
 define <16 x i8> @test_int_x86_xop_vpshlb(<16 x i8> %a0, <16 x i8> %a1) {
-  ; CHECK: vpshlb
+; CHECK-LABEL: test_int_x86_xop_vpshlb:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpshlb %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retq
   %res = call <16 x i8> @llvm.x86.xop.vpshlb(<16 x i8> %a0, <16 x i8> %a1) ;
   ret <16 x i8> %res
 }
 declare <16 x i8> @llvm.x86.xop.vpshlb(<16 x i8>, <16 x i8>) nounwind readnone
 
 define <4 x i32> @test_int_x86_xop_vpshld(<4 x i32> %a0, <4 x i32> %a1) {
-  ; CHECK: vpshld
+; CHECK-LABEL: test_int_x86_xop_vpshld:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpshld %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retq
   %res = call <4 x i32> @llvm.x86.xop.vpshld(<4 x i32> %a0, <4 x i32> %a1) ;
   ret <4 x i32> %res
 }
 declare <4 x i32> @llvm.x86.xop.vpshld(<4 x i32>, <4 x i32>) nounwind readnone
 
 define <2 x i64> @test_int_x86_xop_vpshlq(<2 x i64> %a0, <2 x i64> %a1) {
-  ; CHECK: vpshlq
+; CHECK-LABEL: test_int_x86_xop_vpshlq:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpshlq %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retq
   %res = call <2 x i64> @llvm.x86.xop.vpshlq(<2 x i64> %a0, <2 x i64> %a1) ;
   ret <2 x i64> %res
 }
 declare <2 x i64> @llvm.x86.xop.vpshlq(<2 x i64>, <2 x i64>) nounwind readnone
 
 define <8 x i16> @test_int_x86_xop_vpshlw(<8 x i16> %a0, <8 x i16> %a1) {
-  ; CHECK: vpshlw
+; CHECK-LABEL: test_int_x86_xop_vpshlw:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpshlw %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retq
   %res = call <8 x i16> @llvm.x86.xop.vpshlw(<8 x i16> %a0, <8 x i16> %a1) ;
   ret <8 x i16> %res
 }
 define <8 x i16> @test_int_x86_xop_vpshlw_rm(<8 x i16> %a0, <8 x i16>* %a1) {
-  ; CHECK-NOT: vmovaps
-  ; CHECK: vpshlw
+; CHECK-LABEL: test_int_x86_xop_vpshlw_rm:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpshlw (%rdi), %xmm0, %xmm0
+; CHECK-NEXT:    retq
   %vec = load <8 x i16>, <8 x i16>* %a1
   %res = call <8 x i16> @llvm.x86.xop.vpshlw(<8 x i16> %a0, <8 x i16> %vec) ;
   ret <8 x i16> %res
 }
 define <8 x i16> @test_int_x86_xop_vpshlw_mr(<8 x i16>* %a0, <8 x i16> %a1) {
-  ; CHECK-NOT: vmovaps
-  ; CHECK: vpshlw
+; CHECK-LABEL: test_int_x86_xop_vpshlw_mr:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpshlw %xmm0, (%rdi), %xmm0
+; CHECK-NEXT:    retq
   %vec = load <8 x i16>, <8 x i16>* %a0
   %res = call <8 x i16> @llvm.x86.xop.vpshlw(<8 x i16> %vec, <8 x i16> %a1) ;
   ret <8 x i16> %res
@@ -903,14 +1268,18 @@ define <8 x i16> @test_int_x86_xop_vpshlw_mr(<8 x i16>* %a0, <8 x i16> %a1) {
 declare <8 x i16> @llvm.x86.xop.vpshlw(<8 x i16>, <8 x i16>) nounwind readnone
 
 define <4 x float> @test_int_x86_xop_vfrcz_ss(<4 x float> %a0) {
-  ; CHECK-NOT: mov
-  ; CHECK: vfrczss
+; CHECK-LABEL: test_int_x86_xop_vfrcz_ss:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vfrczss %xmm0, %xmm0
+; CHECK-NEXT:    retq
   %res = call <4 x float> @llvm.x86.xop.vfrcz.ss(<4 x float> %a0) ;
   ret <4 x float> %res
 }
 define <4 x float> @test_int_x86_xop_vfrcz_ss_mem(float* %a0) {
-  ; CHECK-NOT: mov
-  ; CHECK: vfrczss
+; CHECK-LABEL: test_int_x86_xop_vfrcz_ss_mem:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vfrczss (%rdi), %xmm0
+; CHECK-NEXT:    retq
   %elem = load float, float* %a0
   %vec = insertelement <4 x float> undef, float %elem, i32 0
   %res = call <4 x float> @llvm.x86.xop.vfrcz.ss(<4 x float> %vec) ;
@@ -919,14 +1288,18 @@ define <4 x float> @test_int_x86_xop_vfrcz_ss_mem(float* %a0) {
 declare <4 x float> @llvm.x86.xop.vfrcz.ss(<4 x float>) nounwind readnone
 
 define <2 x double> @test_int_x86_xop_vfrcz_sd(<2 x double> %a0) {
-  ; CHECK-NOT: mov
-  ; CHECK: vfrczsd
+; CHECK-LABEL: test_int_x86_xop_vfrcz_sd:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vfrczsd %xmm0, %xmm0
+; CHECK-NEXT:    retq
   %res = call <2 x double> @llvm.x86.xop.vfrcz.sd(<2 x double> %a0) ;
   ret <2 x double> %res
 }
 define <2 x double> @test_int_x86_xop_vfrcz_sd_mem(double* %a0) {
-  ; CHECK-NOT: mov
-  ; CHECK: vfrczsd
+; CHECK-LABEL: test_int_x86_xop_vfrcz_sd_mem:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vfrczsd (%rdi), %xmm0
+; CHECK-NEXT:    retq
   %elem = load double, double* %a0
   %vec = insertelement <2 x double> undef, double %elem, i32 0
   %res = call <2 x double> @llvm.x86.xop.vfrcz.sd(<2 x double> %vec) ;
@@ -935,13 +1308,18 @@ define <2 x double> @test_int_x86_xop_vfrcz_sd_mem(double* %a0) {
 declare <2 x double> @llvm.x86.xop.vfrcz.sd(<2 x double>) nounwind readnone
 
 define <2 x double> @test_int_x86_xop_vfrcz_pd(<2 x double> %a0) {
-  ; CHECK: vfrczpd
+; CHECK-LABEL: test_int_x86_xop_vfrcz_pd:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vfrczpd %xmm0, %xmm0
+; CHECK-NEXT:    retq
   %res = call <2 x double> @llvm.x86.xop.vfrcz.pd(<2 x double> %a0) ;
   ret <2 x double> %res
 }
 define <2 x double> @test_int_x86_xop_vfrcz_pd_mem(<2 x double>* %a0) {
-  ; CHECK-NOT: vmovaps
-  ; CHECK: vfrczpd
+; CHECK-LABEL: test_int_x86_xop_vfrcz_pd_mem:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vfrczpd (%rdi), %xmm0
+; CHECK-NEXT:    retq
   %vec = load <2 x double>, <2 x double>* %a0
   %res = call <2 x double> @llvm.x86.xop.vfrcz.pd(<2 x double> %vec) ;
   ret <2 x double> %res
@@ -949,15 +1327,18 @@ define <2 x double> @test_int_x86_xop_vfrcz_pd_mem(<2 x double>* %a0) {
 declare <2 x double> @llvm.x86.xop.vfrcz.pd(<2 x double>) nounwind readnone
 
 define <4 x double> @test_int_x86_xop_vfrcz_pd_256(<4 x double> %a0) {
-  ; CHECK: vfrczpd
-  ; CHECK: ymm
+; CHECK-LABEL: test_int_x86_xop_vfrcz_pd_256:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vfrczpd %ymm0, %ymm0
+; CHECK-NEXT:    retq
   %res = call <4 x double> @llvm.x86.xop.vfrcz.pd.256(<4 x double> %a0) ;
   ret <4 x double> %res
 }
 define <4 x double> @test_int_x86_xop_vfrcz_pd_256_mem(<4 x double>* %a0) {
-  ; CHECK-NOT: vmovaps
-  ; CHECK: vfrczpd
-  ; CHECK: ymm
+; CHECK-LABEL: test_int_x86_xop_vfrcz_pd_256_mem:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vfrczpd (%rdi), %ymm0
+; CHECK-NEXT:    retq
   %vec = load <4 x double>, <4 x double>* %a0
   %res = call <4 x double> @llvm.x86.xop.vfrcz.pd.256(<4 x double> %vec) ;
   ret <4 x double> %res
@@ -965,13 +1346,18 @@ define <4 x double> @test_int_x86_xop_vfrcz_pd_256_mem(<4 x double>* %a0) {
 declare <4 x double> @llvm.x86.xop.vfrcz.pd.256(<4 x double>) nounwind readnone
 
 define <4 x float> @test_int_x86_xop_vfrcz_ps(<4 x float> %a0) {
-  ; CHECK: vfrczps
+; CHECK-LABEL: test_int_x86_xop_vfrcz_ps:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vfrczps %xmm0, %xmm0
+; CHECK-NEXT:    retq
   %res = call <4 x float> @llvm.x86.xop.vfrcz.ps(<4 x float> %a0) ;
   ret <4 x float> %res
 }
 define <4 x float> @test_int_x86_xop_vfrcz_ps_mem(<4 x float>* %a0) {
-  ; CHECK-NOT: vmovaps
-  ; CHECK: vfrczps
+; CHECK-LABEL: test_int_x86_xop_vfrcz_ps_mem:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vfrczps (%rdi), %xmm0
+; CHECK-NEXT:    retq
   %vec = load <4 x float>, <4 x float>* %a0
   %res = call <4 x float> @llvm.x86.xop.vfrcz.ps(<4 x float> %vec) ;
   ret <4 x float> %res
@@ -979,15 +1365,18 @@ define <4 x float> @test_int_x86_xop_vfrcz_ps_mem(<4 x float>* %a0) {
 declare <4 x float> @llvm.x86.xop.vfrcz.ps(<4 x float>) nounwind readnone
 
 define <8 x float> @test_int_x86_xop_vfrcz_ps_256(<8 x float> %a0) {
-  ; CHECK: vfrczps
-  ; CHECK: ymm
+; CHECK-LABEL: test_int_x86_xop_vfrcz_ps_256:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vfrczps %ymm0, %ymm0
+; CHECK-NEXT:    retq
   %res = call <8 x float> @llvm.x86.xop.vfrcz.ps.256(<8 x float> %a0) ;
   ret <8 x float> %res
 }
 define <8 x float> @test_int_x86_xop_vfrcz_ps_256_mem(<8 x float>* %a0) {
-  ; CHECK-NOT: vmovaps
-  ; CHECK: vfrczps
-  ; CHECK: ymm
+; CHECK-LABEL: test_int_x86_xop_vfrcz_ps_256_mem:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vfrczps (%rdi), %ymm0
+; CHECK-NEXT:    retq
   %vec = load <8 x float>, <8 x float>* %a0
   %res = call <8 x float> @llvm.x86.xop.vfrcz.ps.256(<8 x float> %vec) ;
   ret <8 x float> %res
@@ -995,56 +1384,80 @@ define <8 x float> @test_int_x86_xop_vfrcz_ps_256_mem(<8 x float>* %a0) {
 declare <8 x float> @llvm.x86.xop.vfrcz.ps.256(<8 x float>) nounwind readnone
 
 define <16 x i8> @test_int_x86_xop_vpcomb(<16 x i8> %a0, <16 x i8> %a1) {
-  ; CHECK:vpcomb
+; CHECK-LABEL: test_int_x86_xop_vpcomb:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpcomltb %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retq
   %res = call <16 x i8> @llvm.x86.xop.vpcomb(<16 x i8> %a0, <16 x i8> %a1, i8 0) ;
   ret <16 x i8> %res
 }
 declare <16 x i8> @llvm.x86.xop.vpcomb(<16 x i8>, <16 x i8>, i8) nounwind readnone
 
 define <8 x i16> @test_int_x86_xop_vpcomw(<8 x i16> %a0, <8 x i16> %a1) {
-  ; CHECK: vpcomw
+; CHECK-LABEL: test_int_x86_xop_vpcomw:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpcomltw %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retq
   %res = call <8 x i16> @llvm.x86.xop.vpcomw(<8 x i16> %a0, <8 x i16> %a1, i8 0) ;
   ret <8 x i16> %res
 }
 declare <8 x i16> @llvm.x86.xop.vpcomw(<8 x i16>, <8 x i16>, i8) nounwind readnone
 
 define <4 x i32> @test_int_x86_xop_vpcomd(<4 x i32> %a0, <4 x i32> %a1) {
-  ; CHECK: vpcomd
+; CHECK-LABEL: test_int_x86_xop_vpcomd:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpcomltd %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retq
   %res = call <4 x i32> @llvm.x86.xop.vpcomd(<4 x i32> %a0, <4 x i32> %a1, i8 0) ;
   ret <4 x i32> %res
 }
 declare <4 x i32> @llvm.x86.xop.vpcomd(<4 x i32>, <4 x i32>, i8) nounwind readnone
 
 define <2 x i64> @test_int_x86_xop_vpcomq(<2 x i64> %a0, <2 x i64> %a1) {
-  ; CHECK: vpcomq
+; CHECK-LABEL: test_int_x86_xop_vpcomq:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpcomltq %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retq
   %res = call <2 x i64> @llvm.x86.xop.vpcomq(<2 x i64> %a0, <2 x i64> %a1, i8 0) ;
   ret <2 x i64> %res
 }
 declare <2 x i64> @llvm.x86.xop.vpcomq(<2 x i64>, <2 x i64>, i8) nounwind readnone
 
 define <16 x i8> @test_int_x86_xop_vpcomub(<16 x i8> %a0, <16 x i8> %a1) {
-  ; CHECK:vpcomub
+; CHECK-LABEL: test_int_x86_xop_vpcomub:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpcomltub %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retq
   %res = call <16 x i8> @llvm.x86.xop.vpcomub(<16 x i8> %a0, <16 x i8> %a1, i8 0) ;
   ret <16 x i8> %res
 }
 declare <16 x i8> @llvm.x86.xop.vpcomub(<16 x i8>, <16 x i8>, i8) nounwind readnone
 
 define <8 x i16> @test_int_x86_xop_vpcomuw(<8 x i16> %a0, <8 x i16> %a1) {
-  ; CHECK: vpcomuw
+; CHECK-LABEL: test_int_x86_xop_vpcomuw:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpcomltuw %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retq
   %res = call <8 x i16> @llvm.x86.xop.vpcomuw(<8 x i16> %a0, <8 x i16> %a1, i8 0) ;
   ret <8 x i16> %res
 }
 declare <8 x i16> @llvm.x86.xop.vpcomuw(<8 x i16>, <8 x i16>, i8) nounwind readnone
 
 define <4 x i32> @test_int_x86_xop_vpcomud(<4 x i32> %a0, <4 x i32> %a1) {
-  ; CHECK: vpcomud
+; CHECK-LABEL: test_int_x86_xop_vpcomud:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpcomltud %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retq
   %res = call <4 x i32> @llvm.x86.xop.vpcomud(<4 x i32> %a0, <4 x i32> %a1, i8 0) ;
   ret <4 x i32> %res
 }
 declare <4 x i32> @llvm.x86.xop.vpcomud(<4 x i32>, <4 x i32>, i8) nounwind readnone
 
 define <2 x i64> @test_int_x86_xop_vpcomuq(<2 x i64> %a0, <2 x i64> %a1) {
-  ; CHECK: vpcomuq
+; CHECK-LABEL: test_int_x86_xop_vpcomuq:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpcomltuq %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retq
   %res = call <2 x i64> @llvm.x86.xop.vpcomuq(<2 x i64> %a0, <2 x i64> %a1, i8 0) ;
   ret <2 x i64> %res
 }