From: Michael Hennerich Date: Thu, 12 Jul 2007 03:58:44 +0000 (+0800) Subject: Blackfin arch: There is no CDPRIO Bit in the EBIU_AMGCTL Register of BF54x arch X-Git-Tag: v3.12-rc1~28705^2~14 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=9be343c5bcd1cf285c2150f363bc9dd7aab8b7fb;p=kernel%2Fkernel-generic.git Blackfin arch: There is no CDPRIO Bit in the EBIU_AMGCTL Register of BF54x arch However there are similar things in the EBIU_DDRQUE Register Signed-off-by: Michael Hennerich Signed-off-by: Bryan Wu --- diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig index e01bfc7..6d23bcc 100644 --- a/arch/blackfin/Kconfig +++ b/arch/blackfin/Kconfig @@ -729,6 +729,7 @@ config C_AMCKEN config C_CDPRIO bool "DMA has priority over core for ext. accesses" + depends on !BF54x default n config C_B0PEN diff --git a/include/asm-blackfin/mach-bf548/bf548.h b/include/asm-blackfin/mach-bf548/bf548.h index 163c79e..9498313 100644 --- a/include/asm-blackfin/mach-bf548/bf548.h +++ b/include/asm-blackfin/mach-bf548/bf548.h @@ -32,16 +32,6 @@ #define SUPPORTED_REVID 0 -/* Masks for generic ERROR IRQ demultiplexing used in int-priority-sc.c */ - -#define SPI_ERR_MASK (TXCOL | RBSY | MODF | TXE) /* SPI_STAT */ -#define SPORT_ERR_MASK (ROVF | RUVF | TOVF | TUVF) /* SPORTx_STAT */ -#define PPI_ERR_MASK (0xFFFF & ~FLD) /* PPI_STATUS */ -#define UART_ERR_MASK_STAT1 (0x4) /* UARTx_IIR */ -#define UART_ERR_MASK_STAT0 (0x2) /* UARTx_IIR */ -#define CAN_ERR_MASK (EWTIF | EWRIF | EPIF | BOIF | WUIF | UIAIF | AAIF | \ - RMLIF | UCEIF | EXTIF | ADIF) /* CAN_GIF */ - #define OFFSET_(x) ((x) & 0x0000FFFF) /*some misc defines*/ @@ -113,13 +103,8 @@ #else #define V_AMCKEN 0x0 #endif -#ifdef CONFIG_C_CDPRIO -#define V_CDPRIO 0x100 -#else -#define V_CDPRIO 0x0 -#endif -#define AMGCTLVAL (V_AMBEN | V_AMCKEN | V_CDPRIO) +#define AMGCTLVAL (V_AMBEN | V_AMCKEN) #define MAX_VC 650000000 #define MIN_VC 50000000