From: Jim Grosbach Date: Sat, 23 Feb 2013 00:52:09 +0000 (+0000) Subject: ARM: Convenience aliases for 'srs*' instructions. X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=9be2d71512f809b56cce915ee01f540d7880525e;p=platform%2Fupstream%2Fllvm.git ARM: Convenience aliases for 'srs*' instructions. Handle an implied 'sp' operand. rdar://11466783 llvm-svn: 175940 --- diff --git a/llvm/lib/Target/ARM/ARMInstrInfo.td b/llvm/lib/Target/ARM/ARMInstrInfo.td index c938c41..9409f35 100644 --- a/llvm/lib/Target/ARM/ARMInstrInfo.td +++ b/llvm/lib/Target/ARM/ARMInstrInfo.td @@ -2103,6 +2103,18 @@ def SRSIB_UPD : SRSI<1, "srsib\tsp!, $mode"> { let Inst{24-23} = 0b11; } +def : ARMInstAlias<"srsda $mode", (SRSDA imm0_31:$mode)>; +def : ARMInstAlias<"srsda $mode!", (SRSDA_UPD imm0_31:$mode)>; + +def : ARMInstAlias<"srsdb $mode", (SRSDB imm0_31:$mode)>; +def : ARMInstAlias<"srsdb $mode!", (SRSDB_UPD imm0_31:$mode)>; + +def : ARMInstAlias<"srsia $mode", (SRSIA imm0_31:$mode)>; +def : ARMInstAlias<"srsia $mode!", (SRSIA_UPD imm0_31:$mode)>; + +def : ARMInstAlias<"srsib $mode", (SRSIB imm0_31:$mode)>; +def : ARMInstAlias<"srsib $mode!", (SRSIB_UPD imm0_31:$mode)>; + // Return From Exception class RFEI : XI<(outs), (ins GPR:$Rn), AddrModeNone, 4, IndexModeNone, BrFrm, diff --git a/llvm/lib/Target/ARM/ARMInstrThumb2.td b/llvm/lib/Target/ARM/ARMInstrThumb2.td index cf8b302..c9d709e 100644 --- a/llvm/lib/Target/ARM/ARMInstrThumb2.td +++ b/llvm/lib/Target/ARM/ARMInstrThumb2.td @@ -3481,6 +3481,13 @@ def t2SRSIA_UPD : T2SRS<0b11, 1, (outs), (ins imm0_31:$mode), NoItinerary, def t2SRSIA : T2SRS<0b11, 0, (outs), (ins imm0_31:$mode), NoItinerary, "srsia","\tsp, $mode", []>; + +def : t2InstAlias<"srsdb${p} $mode", (t2SRSDB imm0_31:$mode, pred:$p)>; +def : t2InstAlias<"srsdb${p} $mode!", (t2SRSDB_UPD imm0_31:$mode, pred:$p)>; + +def : t2InstAlias<"srsia${p} $mode", (t2SRSIA imm0_31:$mode, pred:$p)>; +def : t2InstAlias<"srsia${p} $mode!", (t2SRSIA_UPD imm0_31:$mode, pred:$p)>; + // Return From Exception is a system instruction. class T2RFE op31_20, dag oops, dag iops, InstrItinClass itin, string opc, string asm, list pattern> diff --git a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp index c95cc1b..6c678fd 100644 --- a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp +++ b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp @@ -4625,6 +4625,15 @@ bool ARMAsmParser::parseOperand(SmallVectorImpl &Operands, } E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E)); + + // There can be a trailing '!' on operands that we want as a separate + // '!' Token operand. Handle that here. For example, the compatibilty + // alias for 'srsdb sp!, #imm' is 'srsdb #imm!'. + if (Parser.getTok().is(AsmToken::Exclaim)) { + Operands.push_back(ARMOperand::CreateToken(Parser.getTok().getString(), + Parser.getTok().getLoc())); + Parser.Lex(); // Eat exclaim token + } return false; } // w/ a ':' after the '#', it's just like a plain ':'. diff --git a/llvm/test/MC/ARM/basic-arm-instructions.s b/llvm/test/MC/ARM/basic-arm-instructions.s index 5c2a214..45ea278 100644 --- a/llvm/test/MC/ARM/basic-arm-instructions.s +++ b/llvm/test/MC/ARM/basic-arm-instructions.s @@ -2087,6 +2087,49 @@ Lforward: @ CHECK: srsia sp, #5 @ encoding: [0x05,0x05,0xcd,0xf8] @ CHECK: srsia sp!, #5 @ encoding: [0x05,0x05,0xed,0xf8] +@ Compatibility aliases. + srsda #5 + srsdb #1 + srsia #0 + srsib #15 + + srsda #31! + srsdb #19! + srsia #2! + srsib #14! + + srsfa #11 + srsea #10 + srsfd #9 + srsed #5 + + srsfa #5! + srsea #5! + srsfd #5! + srsed #5! + + srs #5 + srs #5! + +@ CHECK: srsda sp, #5 @ encoding: [0x05,0x05,0x4d,0xf8] +@ CHECK: srsdb sp, #1 @ encoding: [0x01,0x05,0x4d,0xf9] +@ CHECK: srsia sp, #0 @ encoding: [0x00,0x05,0xcd,0xf8] +@ CHECK: srsib sp, #15 @ encoding: [0x0f,0x05,0xcd,0xf9] +@ CHECK: srsda sp!, #31 @ encoding: [0x1f,0x05,0x6d,0xf8] +@ CHECK: srsdb sp!, #19 @ encoding: [0x13,0x05,0x6d,0xf9] +@ CHECK: srsia sp!, #2 @ encoding: [0x02,0x05,0xed,0xf8] +@ CHECK: srsib sp!, #14 @ encoding: [0x0e,0x05,0xed,0xf9] +@ CHECK: srsda sp, #11 @ encoding: [0x0b,0x05,0x4d,0xf8] +@ CHECK: srsdb sp, #10 @ encoding: [0x0a,0x05,0x4d,0xf9] +@ CHECK: srsia sp, #9 @ encoding: [0x09,0x05,0xcd,0xf8] +@ CHECK: srsib sp, #5 @ encoding: [0x05,0x05,0xcd,0xf9] +@ CHECK: srsda sp!, #5 @ encoding: [0x05,0x05,0x6d,0xf8] +@ CHECK: srsdb sp!, #5 @ encoding: [0x05,0x05,0x6d,0xf9] +@ CHECK: srsia sp!, #5 @ encoding: [0x05,0x05,0xed,0xf8] +@ CHECK: srsib sp!, #5 @ encoding: [0x05,0x05,0xed,0xf9] +@ CHECK: srsia sp, #5 @ encoding: [0x05,0x05,0xcd,0xf8] +@ CHECK: srsia sp!, #5 @ encoding: [0x05,0x05,0xed,0xf8] + @------------------------------------------------------------------------------ @ SSAT diff --git a/llvm/test/MC/ARM/basic-thumb2-instructions.s b/llvm/test/MC/ARM/basic-thumb2-instructions.s index d495c91..9278a2a 100644 --- a/llvm/test/MC/ARM/basic-thumb2-instructions.s +++ b/llvm/test/MC/ARM/basic-thumb2-instructions.s @@ -2352,6 +2352,32 @@ _func: @ CHECK: srsia sp, #5 @ encoding: [0x8d,0xe9,0x05,0xc0] @ CHECK: srsia sp!, #5 @ encoding: [0xad,0xe9,0x05,0xc0] + srsdb #1 + srsia #0 + + srsdb #19! + srsia #2! + + srsea #10 + srsfd #9 + + srsea #5! + srsfd #5! + + srs #5 + srs #5! + +@ CHECK: srsdb sp, #1 @ encoding: [0x0d,0xe8,0x01,0xc0] +@ CHECK: srsia sp, #0 @ encoding: [0x8d,0xe9,0x00,0xc0] +@ CHECK: srsdb sp!, #19 @ encoding: [0x2d,0xe8,0x13,0xc0] +@ CHECK: srsia sp!, #2 @ encoding: [0xad,0xe9,0x02,0xc0] +@ CHECK: srsdb sp, #10 @ encoding: [0x0d,0xe8,0x0a,0xc0] +@ CHECK: srsia sp, #9 @ encoding: [0x8d,0xe9,0x09,0xc0] +@ CHECK: srsdb sp!, #5 @ encoding: [0x2d,0xe8,0x05,0xc0] +@ CHECK: srsia sp!, #5 @ encoding: [0xad,0xe9,0x05,0xc0] +@ CHECK: srsia sp, #5 @ encoding: [0x8d,0xe9,0x05,0xc0] +@ CHECK: srsia sp!, #5 @ encoding: [0xad,0xe9,0x05,0xc0] + @------------------------------------------------------------------------------ @ SSAT