From: wangpc <pc.wang@linux.alibaba.com>
Date: Wed, 18 Jan 2023 06:24:45 +0000 (+0800)
Subject: [RISCV][NFC] Use uncompressInst to relax instructions
X-Git-Tag: upstream/17.0.6~20607
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=9bb7a38a6943dd3805b1c133f25cf1459416fbed;p=platform%2Fupstream%2Fllvm.git

[RISCV][NFC] Use uncompressInst to relax instructions

As the TODO said, we can just use generated uncompressInst to
relax instructions.

Reviewed By: craig.topper, kito-cheng

Differential Revision: https://reviews.llvm.org/D141834
---

diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
index 150b9e7..892c406 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
@@ -167,36 +167,17 @@ bool RISCVAsmBackend::fixupNeedsRelaxationAdvanced(const MCFixup &Fixup,
 
 void RISCVAsmBackend::relaxInstruction(MCInst &Inst,
                                        const MCSubtargetInfo &STI) const {
-  // TODO: replace this with call to auto generated uncompressinstr() function.
   MCInst Res;
   switch (Inst.getOpcode()) {
   default:
     llvm_unreachable("Opcode not expected!");
   case RISCV::C_BEQZ:
-    // c.beqz $rs1, $imm -> beq $rs1, X0, $imm.
-    Res.setOpcode(RISCV::BEQ);
-    Res.addOperand(Inst.getOperand(0));
-    Res.addOperand(MCOperand::createReg(RISCV::X0));
-    Res.addOperand(Inst.getOperand(1));
-    break;
   case RISCV::C_BNEZ:
-    // c.bnez $rs1, $imm -> bne $rs1, X0, $imm.
-    Res.setOpcode(RISCV::BNE);
-    Res.addOperand(Inst.getOperand(0));
-    Res.addOperand(MCOperand::createReg(RISCV::X0));
-    Res.addOperand(Inst.getOperand(1));
-    break;
   case RISCV::C_J:
-    // c.j $imm -> jal X0, $imm.
-    Res.setOpcode(RISCV::JAL);
-    Res.addOperand(MCOperand::createReg(RISCV::X0));
-    Res.addOperand(Inst.getOperand(0));
-    break;
   case RISCV::C_JAL:
-    // c.jal $imm -> jal X1, $imm.
-    Res.setOpcode(RISCV::JAL);
-    Res.addOperand(MCOperand::createReg(RISCV::X1));
-    Res.addOperand(Inst.getOperand(0));
+    bool Success = RISCVRVC::uncompress(Res, Inst, STI);
+    assert(Success && "Can't uncompress instruction");
+    (void)Success;
     break;
   }
   Inst = std::move(Res);