From: Jason Ekstrand <jason.ekstrand@intel.com>
Date: Fri, 3 Nov 2017 01:30:04 +0000 (-0700)
Subject: intel/fs/nir: Setup immediates based on type in i2b and f2b
X-Git-Tag: upstream/18.1.0~4379
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=9bb34892bf99a6f2285f792519f51cefe5c219ee;p=platform%2Fupstream%2Fmesa.git

intel/fs/nir: Setup immediates based on type in i2b and f2b

Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
---

diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp
index 2f47b02..99e652a 100644
--- a/src/intel/compiler/brw_fs_nir.cpp
+++ b/src/intel/compiler/brw_fs_nir.cpp
@@ -1125,12 +1125,13 @@ fs_visitor::nir_emit_alu(const fs_builder &bld, nir_alu_instr *instr)
          if (instr->op == nir_op_f2b) {
             zero = vgrf(glsl_type::double_type);
             tmp = vgrf(glsl_type::double_type);
+            bld.MOV(zero, setup_imm_df(bld, 0.0));
          } else {
             zero = vgrf(glsl_type::int64_t_type);
             tmp = vgrf(glsl_type::int64_t_type);
+            bld.MOV(zero, brw_imm_q(0));
          }
 
-         bld.MOV(zero, setup_imm_df(bld, 0.0));
          /* A SIMD16 execution needs to be split in two instructions, so use
           * a vgrf instead of the flag register as dst so instruction splitting
           * works