From: Palmer Dabbelt Date: Thu, 9 Mar 2023 23:22:05 +0000 (-0800) Subject: Merge patch series "riscv: asid: switch to alternative way to fix stale TLB entries" X-Git-Tag: v6.6.7~3124^2~8 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=9b7fef255c80db8fc33fc06f2ad6d8e3ced1389b;p=platform%2Fkernel%2Flinux-starfive.git Merge patch series "riscv: asid: switch to alternative way to fix stale TLB entries" Sergey Matyukevich says: Some time ago two different patches have been posted to fix stale TLB entries that caused applications crashes. The patch [0] suggested 'aggregating' mm_cpumask, i.e. current cpu is not cleared for the switched-out task in switch_mm function. For additional explanations see the commit message by Guo Ren. The same approach is used by arc architecture, so another good comment is for switch_mm in arch/arc/include/asm/mmu_context.h. The patch [1] attempted to reduce the number of TLB flushes by deferring (and possibly avoiding) them for CPUs not running the task. Patch [1] has been merged. However we already have two bug reports from different vendors. So apparently something is missing in the approach suggested in [1]. In both cases the patch [0] fixed the issue. This patch series reverts [1] and replaces it by [0]. [0] https://lore.kernel.org/linux-riscv/20221111075902.798571-1-guoren@kernel.org/ [1] https://lore.kernel.org/linux-riscv/20220829205219.283543-1-geomatsi@gmail.com/ * b4-shazam-merge: riscv: asid: Fixup stale TLB entry cause application crash Revert "riscv: mm: notify remote harts about mmu cache updates" Link: https://lore.kernel.org/r/20230226150137.1919750-1-geomatsi@gmail.com Signed-off-by: Palmer Dabbelt --- 9b7fef255c80db8fc33fc06f2ad6d8e3ced1389b