From: Nick Clifton Date: Fri, 23 Aug 2013 07:54:19 +0000 (+0000) Subject: PR binutils/15834 X-Git-Tag: binutils-2_24-branchpoint~199 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=9aff4b7ac12edba0c170c2a55763c3973b708749;p=external%2Fbinutils.git PR binutils/15834 Fix typos: --- bfd/bfdio.c | 2 +- bfd/elf32-spu.c | 2 +- bfd/elfnn-aarch64.c | 2 +- binutils/od-xcoff.c | 2 +- config/tcl.m4 | 2 +- gas/config/tc-ia64.c | 2 +- gas/config/tc-sparc.c | 2 +- gas/config/tc-z80.c | 12 ++++++------ gas/doc/c-i386.texi | 6 +++--- gas/doc/c-m32r.texi | 2 +- gas/testsuite/gas/d10v/instruction_packing.d | 2 +- gas/testsuite/gas/z80/atend.d | 2 +- gold/object.h | 2 +- include/gdb/remote-sim.h | 2 +- include/opcode/ChangeLog | 2 +- include/opcode/i960.h | 2 +- ld/testsuite/ld-mips-elf/mips16-pic-1.inc | 2 +- opcodes/aarch64-asm.c | 2 +- opcodes/aarch64-dis.c | 2 +- opcodes/msp430-dis.c | 2 +- --- diff --git a/bfd/ChangeLog b/bfd/ChangeLog index 824c171..0b07c5e 100644 --- a/bfd/ChangeLog +++ b/bfd/ChangeLog @@ -1,3 +1,10 @@ +2013-08-23 Yuri Chornoivan + + PR binutils/15834 + * bfdio.c: Fix typos. + * elf32-spu.c: Likewise. + * elfnn-aarch64.c: Likewise. + 2013-08-21 Tristan Gingold * coff-rs6000.c (_bfd_xcoff_sizeof_headers): Also count diff --git a/bfd/bfdio.c b/bfd/bfdio.c index be05581..363402e 100644 --- a/bfd/bfdio.c +++ b/bfd/bfdio.c @@ -1,8 +1,6 @@ /* Low-level I/O routines for BFDs. - Copyright 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, - 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2011 - Free Software Foundation, Inc. + Copyright 1990-2013 Free Software Foundation, Inc. Written by Cygnus Support. @@ -89,7 +87,7 @@ real_fopen (const char *filename, const char *modes) #ifdef VMS char *vms_attr; - /* On VMS, fopen allows file attributes as optionnal arguments. + /* On VMS, fopen allows file attributes as optional arguments. We need to use them but we'd better to use the common prototype. In fopen-vms.h, they are separated from the mode with a comma. Split here. */ diff --git a/bfd/elf32-spu.c b/bfd/elf32-spu.c index c72bbfb..86fb33c 100644 --- a/bfd/elf32-spu.c +++ b/bfd/elf32-spu.c @@ -1,7 +1,6 @@ /* SPU specific support for 32-bit ELF - Copyright 2006, 2007, 2008, 2009, 2010, 2011, 2012 - Free Software Foundation, Inc. + Copyright 2006-2013 Free Software Foundation, Inc. This file is part of BFD, the Binary File Descriptor library. @@ -1143,7 +1142,7 @@ count_stub (struct spu_link_hash_table *htab, } /* Support two sizes of overlay stubs, a slower more compact stub of two - intructions, and a faster stub of four instructions. + instructions, and a faster stub of four instructions. Soft-icache stubs are four or eight words. */ static unsigned int diff --git a/bfd/elfnn-aarch64.c b/bfd/elfnn-aarch64.c index 4e6b1ad..bd5f0bf 100644 --- a/bfd/elfnn-aarch64.c +++ b/bfd/elfnn-aarch64.c @@ -6176,7 +6176,7 @@ elfNN_aarch64_create_small_pltn_entry (struct elf_link_hash_entry *h, plt_entry + 4, PG_OFFSET (gotplt_entry_address)); - /* Fill in the the lo12 bits for the add from the pltgot entry. */ + /* Fill in the lo12 bits for the add from the pltgot entry. */ elf_aarch64_update_plt_entry (output_bfd, BFD_RELOC_AARCH64_ADD_LO12, plt_entry + 8, PG_OFFSET (gotplt_entry_address)); diff --git a/binutils/ChangeLog b/binutils/ChangeLog index f3bda63..6d425f2 100644 --- a/binutils/ChangeLog +++ b/binutils/ChangeLog @@ -1,3 +1,8 @@ +2013-08-23 Yuri Chornoivan + + PR binutils/15834 + * od-xcoff.c: Fix typos. + 2013-08-19 Tristan Gingold * nm.c (print_size_symbols): Directly get symbol size. diff --git a/binutils/od-xcoff.c b/binutils/od-xcoff.c index 168a43a..223e192 100644 --- a/binutils/od-xcoff.c +++ b/binutils/od-xcoff.c @@ -1,5 +1,5 @@ /* od-xcoff.c -- dump information about an xcoff object file. - Copyright 2011, 2012 Free Software Foundation, Inc. + Copyright 2011-2013 Free Software Foundation, Inc. Written by Tristan Gingold, Adacore. This file is part of GNU Binutils. @@ -451,7 +451,7 @@ dump_xcoff32_aout_header (bfd *abfd, struct xcoff_dump *data) } if (data->opthdr > sizeof (auxhdr)) { - printf (_("warning: optionnal header size too large (> %d)\n"), + printf (_("warning: optional header size too large (> %d)\n"), (int)sizeof (auxhdr)); sz = sizeof (auxhdr); } diff --git a/gas/ChangeLog b/gas/ChangeLog index fc79d4f..679a7d5 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,6 +1,15 @@ +2013-08-23 Yuri Chornoivan + + PR binutils/15834 + * config/tc-ia64.c: Fix typos. + * config/tc-sparc.c: Likewise. + * config/tc-z80.c: Likewise. + * doc/c-i386.texi: Likewise. + * doc/c-m32r.texi: Likewise. + 2013-08-23 Will Newton - * config/tc-arm.c (do_neon_ldx_stx): Add extra constraints + * config/tc-arm.c: (do_neon_ldx_stx): Add extra constraints for pre-indexed addressing modes. 2013-08-21 Alan Modra diff --git a/gas/config/tc-ia64.c b/gas/config/tc-ia64.c index 0542410..b8ffe4e 100644 --- a/gas/config/tc-ia64.c +++ b/gas/config/tc-ia64.c @@ -1,6 +1,5 @@ /* tc-ia64.c -- Assembler for the HP/Intel IA-64 architecture. - Copyright 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, - 2008, 2009, 2011, 2012, 2013 Free Software Foundation, Inc. + Copyright 1998-2013 Free Software Foundation, Inc. Contributed by David Mosberger-Tang This file is part of GAS, the GNU Assembler. @@ -2978,7 +2977,7 @@ ia64_estimate_size_before_relax (fragS *frag, } /* This function converts a rs_machine_dependent variant frag into a - normal fill frag with the unwind image from the the record list. */ + normal fill frag with the unwind image from the record list. */ void ia64_convert_frag (fragS *frag) { diff --git a/gas/config/tc-sparc.c b/gas/config/tc-sparc.c index d5387be..bcb8464 100644 --- a/gas/config/tc-sparc.c +++ b/gas/config/tc-sparc.c @@ -1,8 +1,5 @@ /* tc-sparc.c -- Assemble for the SPARC - Copyright 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, - 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, - 2011 - Free Software Foundation, Inc. + Copyright 1989-2013 Free Software Foundation, Inc. This file is part of GAS, the GNU Assembler. GAS is free software; you can redistribute it and/or modify @@ -3000,7 +2997,7 @@ sparc_ip (char *str, const struct sparc_opcode **pinsn) return special_case; } - /* Make sure the the hwcaps used by the instruction are + /* Make sure the hwcaps used by the instruction are currently enabled. */ if (hwcaps & ~hwcap_allowed) { diff --git a/gas/config/tc-z80.c b/gas/config/tc-z80.c index d93c155..6d5b621 100644 --- a/gas/config/tc-z80.c +++ b/gas/config/tc-z80.c @@ -1098,7 +1098,7 @@ emit_adc (char prefix, char opcode, const char * args) p = parse_exp (args, &term); if (*p++ != ',') { - error (_("bad intruction syntax")); + error (_("bad instruction syntax")); return p; } @@ -1141,7 +1141,7 @@ emit_add (char prefix, char opcode, const char * args) p = parse_exp (args, &term); if (*p++ != ',') { - error (_("bad intruction syntax")); + error (_("bad instruction syntax")); return p; } @@ -1185,7 +1185,7 @@ emit_bit (char prefix, char opcode, const char * args) p = parse_exp (args, &b); if (*p++ != ',') - error (_("bad intruction syntax")); + error (_("bad instruction syntax")); bn = b.X_add_number; if ((!b.X_md) @@ -1305,7 +1305,7 @@ emit_in (char prefix ATTRIBUTE_UNUSED, char opcode ATTRIBUTE_UNUSED, p = parse_exp (args, ®); if (*p++ != ',') { - error (_("bad intruction syntax")); + error (_("bad instruction syntax")); return p; } @@ -1359,7 +1359,7 @@ emit_out (char prefix ATTRIBUTE_UNUSED, char opcode ATTRIBUTE_UNUSED, p = parse_exp (args, & port); if (*p++ != ',') { - error (_("bad intruction syntax")); + error (_("bad instruction syntax")); return p; } p = parse_exp (p, ®); @@ -1628,7 +1628,7 @@ emit_ld (char prefix_in ATTRIBUTE_UNUSED, char opcode_in ATTRIBUTE_UNUSED, p = parse_exp (args, &dst); if (*p++ != ',') - error (_("bad intruction syntax")); + error (_("bad instruction syntax")); p = parse_exp (p, &src); switch (dst.X_op) diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi index 33fab18..7ca70c9 100644 --- a/gas/doc/c-i386.texi +++ b/gas/doc/c-i386.texi @@ -1,6 +1,4 @@ -@c Copyright 1991, 1992, 1993, 1994, 1995, 1997, 1998, 1999, 2000, -@c 2001, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2011 -@c Free Software Foundation, Inc. +@c Copyright 1991-2013 Free Software Foundation, Inc. @c This is part of the GAS manual. @c For copying conditions, see the file as.texinfo. @c man end @@ -217,12 +215,12 @@ with VEX prefix. @item -msse-check=@var{none} @itemx -msse-check=@var{warning} @itemx -msse-check=@var{error} -These options control if the assembler should check SSE intructions. +These options control if the assembler should check SSE instructions. @option{-msse-check=@var{none}} will make the assembler not to check SSE instructions, which is the default. @option{-msse-check=@var{warning}} -will make the assembler issue a warning for any SSE intruction. +will make the assembler issue a warning for any SSE instruction. @option{-msse-check=@var{error}} will make the assembler issue an error -for any SSE intruction. +for any SSE instruction. @cindex @samp{-mavxscalar=} option, i386 @cindex @samp{-mavxscalar=} option, x86-64 diff --git a/gas/doc/c-m32r.texi b/gas/doc/c-m32r.texi index 7ef313f..abb0728 100644 --- a/gas/doc/c-m32r.texi +++ b/gas/doc/c-m32r.texi @@ -1,6 +1,4 @@ -@c Copyright 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, -@c 2000, 2003, 2004, 2006 -@c Free Software Foundation, Inc. +@c Copyright 1991-2013 Free Software Foundation, Inc. @c This is part of the GAS manual. @c For copying conditions, see the file as.texinfo. @ifset GENERIC @@ -46,7 +44,7 @@ the original instructions. @cindex @samp{-m32rx} option, M32R2 @cindex architecture options, M32R2 @cindex M32R architecture options -This option changes the target processor to the the M32R2 +This option changes the target processor to the M32R2 microprocessor. @item -m32r diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog index 219591a..253b3a5 100644 --- a/gas/testsuite/ChangeLog +++ b/gas/testsuite/ChangeLog @@ -1,3 +1,9 @@ +2013-08-23 Yuri Chornoivan + + PR binutils/15834 + * gas/d10v/instruction_packing.d: Fix typos. + * gas/z80/atend.d: Likewise. + 2013-08-23 Will Newton * testsuite/gas/arm/neon-addressing-bad.l: Add test for diff --git a/gas/testsuite/gas/d10v/instruction_packing.d b/gas/testsuite/gas/d10v/instruction_packing.d index df21b04..8ccb9db 100644 --- a/gas/testsuite/gas/d10v/instruction_packing.d +++ b/gas/testsuite/gas/d10v/instruction_packing.d @@ -1,5 +1,5 @@ #objdump: -Dr -#name: D10V intruction packing +#name: D10V instruction packing #as: -W .*: +file format elf32-d10v diff --git a/gas/testsuite/gas/z80/atend.d b/gas/testsuite/gas/z80/atend.d index e0427b1..fcd3735 100644 --- a/gas/testsuite/gas/z80/atend.d +++ b/gas/testsuite/gas/z80/atend.d @@ -1,5 +1,5 @@ #objdump: -d -#name: index intructions with label as offset +#name: index instructions with label as offset .*: .* diff --git a/gold/ChangeLog b/gold/ChangeLog index 08db459..324d8bc 100644 --- a/gold/ChangeLog +++ b/gold/ChangeLog @@ -1,3 +1,8 @@ +2013-08-23 Yuri Chornoivan + + PR binutils/15834 + * object.h: Fix typos. + 2013-08-16 Roland McGrath * i386.cc (Target_i386_nacl::do_code_fill): New virtual function. diff --git a/gold/object.h b/gold/object.h index ae6d9bf..88263b4 100644 --- a/gold/object.h +++ b/gold/object.h @@ -1178,7 +1178,7 @@ class Relobj : public Object return this->output_sections_[shndx] != NULL; } - // The the output section of the input section with index SHNDX. + // The output section of the input section with index SHNDX. // This is only used currently to remove a section from the link in // relaxation. void diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog index e842f5d..caf7aee 100644 --- a/include/opcode/ChangeLog +++ b/include/opcode/ChangeLog @@ -1,3 +1,8 @@ +2013-08-23 Yuri Chornoivan + + PR binutils/15834 + * i960.h: Fix typos. + 2013-08-19 Richard Sandiford * mips.h: Remove references to "+I" and imm2_expr. @@ -1110,7 +1115,7 @@ 2008-04-28 Adam Nemet - * mips.h (INSN_MACRO): Move it up to the the pinfo macros. + * mips.h (INSN_MACRO): Move it up to the pinfo macros. (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros. 2008-04-14 Edmar Wienskoski diff --git a/include/opcode/i960.h b/include/opcode/i960.h index dc0e78f..7b8e1f5 100644 --- a/include/opcode/i960.h +++ b/include/opcode/i960.h @@ -1,6 +1,6 @@ /* Basic 80960 instruction formats. - Copyright 2001, 2010 Free Software Foundation, Inc. + Copyright 2001-2013 Free Software Foundation, Inc. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by @@ -141,7 +141,7 @@ struct i960_opcode { char operand[3];/* Operand descriptors; same order as assembler instr */ }; -/* Classes of 960 intructions: +/* Classes of 960 instructions: * - each instruction falls into one class. * - each target architecture supports one or more classes. * diff --git a/ld/testsuite/ChangeLog b/ld/testsuite/ChangeLog index feb8b9b..cc05034 100644 --- a/ld/testsuite/ChangeLog +++ b/ld/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2013-08-23 Yuri Chornoivan + + PR binutils/15834 + * ld-mips-elf/mips16-pic-1.inc: Fix typos. + 2013-08-22 Alan Modra * ld-powerpc/powerpc.exp: Substitute for le in options_regsub(ld). diff --git a/ld/testsuite/ld-mips-elf/mips16-pic-1.inc b/ld/testsuite/ld-mips-elf/mips16-pic-1.inc index 9268a07..01bdbdd 100644 --- a/ld/testsuite/ld-mips-elf/mips16-pic-1.inc +++ b/ld/testsuite/ld-mips-elf/mips16-pic-1.inc @@ -1,5 +1,5 @@ # Declare a function called NAME and an __fn_NAME stub for it. - # Make the stub use la_TYPE to load the the target address into $2. + # Make the stub use la_TYPE to load the target address into $2. .macro stub,name,type .set nomips16 .section .mips16.fn.\name, "ax", @progbits diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index af6ba2b..7427f14 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,10 @@ +2013-08-23 Yuri Chornoivan + + PR binutils/15834 + * aarch64-asm.c: Fix typos. + * aarch64-dis.c: Likewise. + * msp430-dis.c: Likewise. + 2013-08-19 Richard Sandiford * micromips-opc.c (micromips_opcodes): Replace "dext" and "dins" diff --git a/opcodes/aarch64-asm.c b/opcodes/aarch64-asm.c index 96396e8..27a4def 100644 --- a/opcodes/aarch64-asm.c +++ b/opcodes/aarch64-asm.c @@ -1,5 +1,5 @@ /* aarch64-asm.c -- AArch64 assembler support. - Copyright 2012, 2013 Free Software Foundation, Inc. + Copyright 2012-2013 Free Software Foundation, Inc. Contributed by ARM Ltd. This file is part of the GNU opcodes library. @@ -31,7 +31,7 @@ N.B. the fields are required to be in such an order than the least signficant field for VALUE comes the first, e.g. the in SQDMLAL , , .[] - is encoded in H:L:M in some cases, the the fields H:L:M should be passed in + is encoded in H:L:M in some cases, the fields H:L:M should be passed in the order of M, L, H. */ static inline void diff --git a/opcodes/aarch64-dis.c b/opcodes/aarch64-dis.c index c757316..c403be8 100644 --- a/opcodes/aarch64-dis.c +++ b/opcodes/aarch64-dis.c @@ -1,5 +1,5 @@ /* aarch64-dis.c -- AArch64 disassembler. - Copyright 2009, 2010, 2011, 2012, 2013 Free Software Foundation, Inc. + Copyright 2009-2013 Free Software Foundation, Inc. Contributed by ARM Ltd. This file is part of the GNU opcodes library. @@ -120,7 +120,7 @@ parse_aarch64_dis_options (const char *options) N.B. the fields are required to be in such an order than the most signficant field for VALUE comes the first, e.g. the in SQDMLAL , , .[] - is encoded in H:L:M in some cases, the the fields H:L:M should be passed in + is encoded in H:L:M in some cases, the fields H:L:M should be passed in the order of H, L, M. */ static inline aarch64_insn diff --git a/opcodes/msp430-dis.c b/opcodes/msp430-dis.c index 46da3cc..c314638 100644 --- a/opcodes/msp430-dis.c +++ b/opcodes/msp430-dis.c @@ -836,7 +836,7 @@ msp430x_calla_instr (disassemble_info * info, break; default: - strcpy (comm1, _("unercognised CALLA addressing mode")); + strcpy (comm1, _("unrecognised CALLA addressing mode")); return -1; }