From: Rhys Perry <pendingchaos02@gmail.com>
Date: Thu, 4 Aug 2022 16:54:56 +0000 (+0100)
Subject: radv: fix 16-bit support in radv_lower_vs_input
X-Git-Tag: upstream/22.3.5~4167
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=9ae13a9bd39e6b71ae0748d1cca598dce13f6306;p=platform%2Fupstream%2Fmesa.git

radv: fix 16-bit support in radv_lower_vs_input

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Fixes: b366fef091d ("radv: optimize the number of loaded components for VS inputs in NIR")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18225>
---

diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 13fd8da..1d77be9 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -3864,9 +3864,10 @@ radv_lower_vs_input(nir_shader *nir, const struct radv_pipeline_key *pipeline_ke
             if (swizzle[i + component] < num_channels) {
                channels[i] = nir_channel(&b, &intrin->dest.ssa, swizzle[idx]);
             } else if (i + component == 3) {
-               channels[i] = is_float ? nir_imm_float(&b, 1.0f) : nir_imm_int(&b, 1u);
+               channels[i] = is_float ? nir_imm_floatN_t(&b, 1.0f, intrin->dest.ssa.bit_size)
+                                      : nir_imm_intN_t(&b, 1u, intrin->dest.ssa.bit_size);
             } else {
-               channels[i] = nir_imm_zero(&b, 1, 32);
+               channels[i] = nir_imm_zero(&b, 1, intrin->dest.ssa.bit_size);
             }
          }