From: Tony Lindgren <tony@atomide.com>
Date: Wed, 4 Mar 2020 16:10:42 +0000 (-0800)
Subject: ARM: dts: Configure interconnect target module for dra7 dispc
X-Git-Tag: v5.15~4151^2^2~2^2~25
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=9a95196c43ab1b6388c4b8a72e1a64d1f20d6046;p=platform%2Fkernel%2Flinux-starfive.git

ARM: dts: Configure interconnect target module for dra7 dispc

We can now probe devices with device tree only configuration using
ti-sysc interconnect target module driver. Let's configure the
module, but keep the legacy "ti,hwmods" peroperty until the child
devices are probing with ti-sysc interconnect driver.

Cc: Jyri Sarha <jsarha@ti.com>
Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Cc: Tomi Valkeinen <tomi.valkeinen@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
---

diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index cf90a0e..594b53a 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -732,15 +732,39 @@
 				#size-cells = <1>;
 				ranges = <0 0 0x800000>;
 
-				dispc@1000 {
-					compatible = "ti,dra7-dispc";
-					reg = <0x1000 0x1000>;
-					interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
-					ti,hwmods = "dss_dispc";
-					clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 8>;
+				target-module@1000 {
+					compatible = "ti,sysc-omap2", "ti,sysc";
+					reg = <0x1000 0x4>,
+					      <0x1010 0x4>,
+					      <0x1014 0x4>;
+					reg-names = "rev", "sysc", "syss";
+					ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+							<SYSC_IDLE_NO>,
+							<SYSC_IDLE_SMART>;
+					ti,sysc-midle = <SYSC_IDLE_FORCE>,
+							<SYSC_IDLE_NO>,
+							<SYSC_IDLE_SMART>;
+					ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+							 SYSC_OMAP2_ENAWAKEUP |
+							 SYSC_OMAP2_SOFTRESET |
+							 SYSC_OMAP2_AUTOIDLE)>;
+					ti,syss-mask = <1>;
+					clocks = <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 8>;
 					clock-names = "fck";
-					/* CTRL_CORE_SMA_SW_1 */
-					syscon-pol = <&scm_conf 0x534>;
+					#address-cells = <1>;
+					#size-cells = <1>;
+					ranges = <0 0x1000 0x1000>;
+
+					dispc@0 {
+						compatible = "ti,dra7-dispc";
+						reg = <0 0x1000>;
+						interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+						ti,hwmods = "dss_dispc";
+						clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 8>;
+						clock-names = "fck";
+						/* CTRL_CORE_SMA_SW_1 */
+						syscon-pol = <&scm_conf 0x534>;
+					};
 				};
 
 				hdmi: encoder@40000 {