From: Connor Abbott <cwabbott0@gmail.com>
Date: Tue, 9 Mar 2021 15:00:15 +0000 (+0100)
Subject: freedreno/registers: Handle typed registers with fields
X-Git-Tag: upstream/21.2.3~6715
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=9a5596d6798c587552e26d53fa6f0acbd649f937;p=platform%2Fupstream%2Fmesa.git

freedreno/registers: Handle typed registers with fields

When a bitset is "inline" it should act as-if the its fields were
inserted into the register itself. However when initializing the
register's bitfield we weren't doing a deep copy of the inline bitfield,
so if the register defined additional fields then they would get added
to the original inline bitfield and any further registers with the same
type would get them. Fix this.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9493>
---

diff --git a/src/freedreno/registers/gen_header.py b/src/freedreno/registers/gen_header.py
index 45b9a3e..e677685 100644
--- a/src/freedreno/registers/gen_header.py
+++ b/src/freedreno/registers/gen_header.py
@@ -105,7 +105,7 @@ class Bitset(object):
 		self.name = name
 		self.inline = False
 		if template:
-			self.fields = template.fields
+			self.fields = template.fields[:]
 		else:
 			self.fields = []
 
@@ -358,7 +358,12 @@ class Parser(object):
 
 	def parse_reg(self, attrs, bit_size):
 		if "type" in attrs and attrs["type"] in self.bitsets:
-			self.current_bitset = self.bitsets[attrs["type"]]
+			bitset = self.bitsets[attrs["type"]]
+			if bitset.inline:
+				self.current_bitset = Bitset(attrs["name"], bitset)
+				self.current_bitset.inline = True
+			else:
+				self.current_bitset = bitset
 		else:
 			self.current_bitset = Bitset(attrs["name"], None)
 			self.current_bitset.inline = True