From: Nathan Sidwell Date: Mon, 23 Apr 2007 07:51:33 +0000 (+0000) Subject: gas/testsuite/ X-Git-Tag: binutils-2_18-branchpoint~973 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=9a2e615a9f06fd8aebee3da95ed551de303719bb;p=external%2Fbinutils.git gas/testsuite/ * gas/m68k/br-isaa.s: New. * gas/m68k/br-isaa.d: New. * gas/m68k/br-isab.s: New. * gas/m68k/br-isab.d: New. * gas/m68k/br-isac.s: New. * gas/m68k/br-isac.d: New. * gas/m68k/all.exp: Adjust. gas/ * config/tc-m68k.c (mcf54455_ctrl): New. (HAVE_LONG_DISP, HAVE_LONG_CALL, HAVE_LONG_COND): New. (m68k_archs): Add isac. (m68k_cpus): Add 54455 family. (m68k_ip): Split Bg into Bb, Bs, Bg. (m68k_elf_final_processing): Add ISA_C. * doc/c-m68k.texi (M680x0 Options): Add isac. include/opcode/ * m68k.h (mcfisa_c): New. (mcfusp, mcf_mask): Adjust. bfd/ * archures.c (bfd_mach_mcf_isa_c, bfd_mach_mcf_isa_c_mac, bfd_mach_mcf_isa_c_emac): New. * elf32-m68k.c (ISAC_PLT_ENTRY_SIZE, elf_isac_plt0_entry, elf_isac_plt_entry, elf_isac_plt_info): New. (elf32_m68k_object_p): Add ISA_C. (elf32_m68k_print_private_bfd_data): Print ISA_C. (elf32_m68k_get_plt_info): Detect ISA_C. * cpu-m68k.c (arch_info): Add ISAC. (m68k_arch_features): Likewise, (bfd_m68k_compatible): ISAs B & C are not compatible. opcodes/ * m68k-opc.c: Mark mcfisa_c instructions. --- diff --git a/bfd/ChangeLog b/bfd/ChangeLog index ad991c8..5758423 100644 --- a/bfd/ChangeLog +++ b/bfd/ChangeLog @@ -1,3 +1,16 @@ +2007-04-23 Nathan Sidwell + + * archures.c (bfd_mach_mcf_isa_c, bfd_mach_mcf_isa_c_mac, + bfd_mach_mcf_isa_c_emac): New. + * elf32-m68k.c (ISAC_PLT_ENTRY_SIZE, elf_isac_plt0_entry, + elf_isac_plt_entry, elf_isac_plt_info): New. + (elf32_m68k_object_p): Add ISA_C. + (elf32_m68k_print_private_bfd_data): Print ISA_C. + (elf32_m68k_get_plt_info): Detect ISA_C. + * cpu-m68k.c (arch_info): Add ISAC. + (m68k_arch_features): Likewise, + (bfd_m68k_compatible): ISAs B & C are not compatible. + 2007-04-21 Nick Clifton * ecoff.c (_bfd_ecoff_write_armap): Initialise rehash. diff --git a/bfd/archures.c b/bfd/archures.c index f43e2e6..3002043 100644 --- a/bfd/archures.c +++ b/bfd/archures.c @@ -97,6 +97,9 @@ DESCRIPTION .#define bfd_mach_mcf_isa_b_float 23 .#define bfd_mach_mcf_isa_b_float_mac 24 .#define bfd_mach_mcf_isa_b_float_emac 25 +.#define bfd_mach_mcf_isa_c 26 +.#define bfd_mach_mcf_isa_c_mac 27 +.#define bfd_mach_mcf_isa_c_emac 28 . bfd_arch_vax, {* DEC Vax *} . bfd_arch_i960, {* Intel 960 *} . {* The order of the following is important. diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h index d34456a..8154435 100644 --- a/bfd/bfd-in2.h +++ b/bfd/bfd-in2.h @@ -1761,6 +1761,9 @@ enum bfd_architecture #define bfd_mach_mcf_isa_b_float 23 #define bfd_mach_mcf_isa_b_float_mac 24 #define bfd_mach_mcf_isa_b_float_emac 25 +#define bfd_mach_mcf_isa_c 26 +#define bfd_mach_mcf_isa_c_mac 27 +#define bfd_mach_mcf_isa_c_emac 28 bfd_arch_vax, /* DEC Vax */ bfd_arch_i960, /* Intel 960 */ /* The order of the following is important. diff --git a/bfd/cpu-m68k.c b/bfd/cpu-m68k.c index 2e6f6c6..7e424a8 100644 --- a/bfd/cpu-m68k.c +++ b/bfd/cpu-m68k.c @@ -76,19 +76,25 @@ static const bfd_arch_info_type arch_info_struct[] = FALSE, &arch_info_struct[24]), N(bfd_mach_mcf_isa_b_float_emac, "m68k:isa-b:float:emac", FALSE, &arch_info_struct[25]), + N(bfd_mach_mcf_isa_c, "m68k:isa-c", + FALSE, &arch_info_struct[26]), + N(bfd_mach_mcf_isa_c_mac, "m68k:isa-c:mac", + FALSE, &arch_info_struct[27]), + N(bfd_mach_mcf_isa_c_emac, "m68k:isa-c:emac", + FALSE, &arch_info_struct[28]), /* Legacy names for CF architectures */ - N(bfd_mach_mcf_isa_a_nodiv, "m68k:5200", FALSE, &arch_info_struct[26]), - N(bfd_mach_mcf_isa_a_mac,"m68k:5206e", FALSE, &arch_info_struct[27]), - N(bfd_mach_mcf_isa_a_mac, "m68k:5307", FALSE, &arch_info_struct[28]), - N(bfd_mach_mcf_isa_b_nousp_mac, "m68k:5407", FALSE, &arch_info_struct[29]), - N(bfd_mach_mcf_isa_aplus_emac, "m68k:528x", FALSE, &arch_info_struct[30]), - N(bfd_mach_mcf_isa_aplus_emac, "m68k:521x", FALSE, &arch_info_struct[31]), - N(bfd_mach_mcf_isa_a_emac, "m68k:5249", FALSE, &arch_info_struct[32]), + N(bfd_mach_mcf_isa_a_nodiv, "m68k:5200", FALSE, &arch_info_struct[29]), + N(bfd_mach_mcf_isa_a_mac,"m68k:5206e", FALSE, &arch_info_struct[30]), + N(bfd_mach_mcf_isa_a_mac, "m68k:5307", FALSE, &arch_info_struct[31]), + N(bfd_mach_mcf_isa_b_nousp_mac, "m68k:5407", FALSE, &arch_info_struct[32]), + N(bfd_mach_mcf_isa_aplus_emac, "m68k:528x", FALSE, &arch_info_struct[33]), + N(bfd_mach_mcf_isa_aplus_emac, "m68k:521x", FALSE, &arch_info_struct[34]), + N(bfd_mach_mcf_isa_a_emac, "m68k:5249", FALSE, &arch_info_struct[35]), N(bfd_mach_mcf_isa_b_float_emac, "m68k:547x", - FALSE, &arch_info_struct[33]), + FALSE, &arch_info_struct[36]), N(bfd_mach_mcf_isa_b_float_emac, "m68k:548x", - FALSE, &arch_info_struct[34]), + FALSE, &arch_info_struct[37]), N(bfd_mach_mcf_isa_b_float_emac, "m68k:cfv4e", FALSE, 0), }; @@ -125,6 +131,9 @@ static const unsigned m68k_arch_features[] = mcfisa_a|mcfhwdiv|mcfisa_b|mcfusp|cfloat, mcfisa_a|mcfhwdiv|mcfisa_b|mcfusp|cfloat|mcfmac, mcfisa_a|mcfhwdiv|mcfisa_b|mcfusp|cfloat|mcfemac, + mcfisa_a|mcfhwdiv|mcfisa_c|mcfusp, + mcfisa_a|mcfhwdiv|mcfisa_c|mcfusp|mcfmac, + mcfisa_a|mcfhwdiv|mcfisa_c|mcfusp|mcfemac, }; /* Return the count of bits set in MASK */ @@ -222,6 +231,10 @@ bfd_m68k_compatible (const bfd_arch_info_type *a, if ((~features & (mcfisa_aa | mcfisa_b)) == 0) return NULL; + /* ISA B and ISA C are incompatible. */ + if ((~features & (mcfisa_b | mcfisa_c)) == 0) + return NULL; + /* MAC and EMAC code cannot be merged. */ if ((~features & (mcfmac | mcfemac)) == 0) return NULL; diff --git a/bfd/elf32-m68k.c b/bfd/elf32-m68k.c index 948a996..6cc0212 100644 --- a/bfd/elf32-m68k.c +++ b/bfd/elf32-m68k.c @@ -300,6 +300,40 @@ static const struct elf_m68k_plt_info elf_isab_plt_info = { elf_isab_plt_entry, { 2, 20 }, 12 }; +#define ISAC_PLT_ENTRY_SIZE 24 + +static const bfd_byte elf_isac_plt0_entry[ISAC_PLT_ENTRY_SIZE] = +{ + 0x20, 0x3c, /* move.l #offset,%d0 */ + 0, 0, 0, 0, /* replaced with .got + 4 - . */ + 0x2e, 0xbb, 0x08, 0xfa, /* move.l (-6,%pc,%d0:l),(%sp) */ + 0x20, 0x3c, /* move.l #offset,%d0 */ + 0, 0, 0, 0, /* replaced with .got + 8 - . */ + 0x20, 0x7b, 0x08, 0xfa, /* move.l (-6,%pc,%d0:l), %a0 */ + 0x4e, 0xd0, /* jmp (%a0) */ + 0x4e, 0x71 /* nop */ +}; + +/* Subsequent entries in a procedure linkage table look like this. */ + +static const bfd_byte elf_isac_plt_entry[ISAC_PLT_ENTRY_SIZE] = +{ + 0x20, 0x3c, /* move.l #offset,%d0 */ + 0, 0, 0, 0, /* replaced with (.got entry) - . */ + 0x20, 0x7b, 0x08, 0xfa, /* move.l (-6,%pc,%d0:l), %a0 */ + 0x4e, 0xd0, /* jmp (%a0) */ + 0x2f, 0x3c, /* move.l #offset,-(%sp) */ + 0, 0, 0, 0, /* replaced with offset into relocation table */ + 0x61, 0xff, /* bsr.l .plt */ + 0, 0, 0, 0 /* replaced with .plt - . */ +}; + +static const struct elf_m68k_plt_info elf_isac_plt_info = { + ISAC_PLT_ENTRY_SIZE, + elf_isac_plt0_entry, { 2, 12}, + elf_isac_plt_entry, { 2, 20 }, 12 +}; + #define CPU32_PLT_ENTRY_SIZE 24 /* Procedure linkage table entries for the cpu32 */ static const bfd_byte elf_cpu32_plt0_entry[CPU32_PLT_ENTRY_SIZE] = @@ -468,6 +502,9 @@ elf32_m68k_object_p (bfd *abfd) case EF_M68K_CF_ISA_B: features |= mcfisa_a|mcfisa_b|mcfhwdiv|mcfusp; break; + case EF_M68K_CF_ISA_C: + features |= mcfisa_a|mcfisa_c|mcfhwdiv|mcfusp; + break; } switch (eflags & EF_M68K_CF_MAC_MASK) { @@ -617,6 +654,9 @@ elf32_m68k_print_private_bfd_data (abfd, ptr) case EF_M68K_CF_ISA_B: isa = "B"; break; + case EF_M68K_CF_ISA_C: + isa = "C"; + break; } fprintf (file, " [isa %s]%s", isa, additional); if (eflags & EF_M68K_CF_FLOAT) @@ -1145,6 +1185,8 @@ elf_m68k_get_plt_info (bfd *output_bfd) return &elf_cpu32_plt_info; if (features & mcfisa_b) return &elf_isab_plt_info; + if (features & mcfisa_c) + return &elf_isac_plt_info; return &elf_m68k_plt_info; } diff --git a/gas/ChangeLog b/gas/ChangeLog index 0985ece..98c4d2c 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,13 @@ +2007-04-23 Nathan Sidwell + + * config/tc-m68k.c (mcf54455_ctrl): New. + (HAVE_LONG_DISP, HAVE_LONG_CALL, HAVE_LONG_COND): New. + (m68k_archs): Add isac. + (m68k_cpus): Add 54455 family. + (m68k_ip): Split Bg into Bb, Bs, Bg. + (m68k_elf_final_processing): Add ISA_C. + * doc/c-m68k.texi (M680x0 Options): Add isac. + 2007-04-22 Alan Modra * read.c (read_a_source_file): Skip multiple spaces to diff --git a/gas/config/tc-m68k.c b/gas/config/tc-m68k.c index cce9b55..fedbafc 100644 --- a/gas/config/tc-m68k.c +++ b/gas/config/tc-m68k.c @@ -268,6 +268,15 @@ static const enum m68k_register mcfv4e_ctrl[] = { ROMBAR /* ROMBAR0 */, RAMBAR /* RAMBAR1 */, 0 }; +static const enum m68k_register mcf54455_ctrl[] = { + CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR, + VBR, PC, RAMBAR1, MBAR, + /* Legacy names */ + TC /* ASID */, BUSCR /* MMUBAR */, + ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */, + MBAR1 /* MBAR */, RAMBAR /* RAMBAR1 */, + 0 +}; static const enum m68k_register mcf5475_ctrl[] = { CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR, VBR, PC, RAMBAR0, RAMBAR1, MBAR, @@ -350,7 +359,14 @@ struct m68k_it #define arch_coldfire_fpu(x) ((x) & cfloat) /* Macros for determining if cpu supports a specific addressing mode. */ -#define HAVE_LONG_BRANCH(x) ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b)) +#define HAVE_LONG_DISP(x) \ + ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b|mcfisa_c)) +#define HAVE_LONG_CALL(x) \ + ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b|mcfisa_c)) +#define HAVE_LONG_COND(x) \ + ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b|mcfisa_c)) +#define HAVE_LONG_BRANCH(x) \ + ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b)) static struct m68k_it the_ins; /* The instruction being assembled. */ @@ -484,6 +500,7 @@ static const struct m68k_cpu m68k_archs[] = {mcfisa_a|mcfhwdiv, NULL, "isaa", 0}, {mcfisa_a|mcfhwdiv|mcfisa_aa|mcfusp, NULL, "isaaplus", 0}, {mcfisa_a|mcfhwdiv|mcfisa_b|mcfusp, NULL, "isab", 0}, + {mcfisa_a|mcfhwdiv|mcfisa_c|mcfusp, NULL, "isac", 0}, {mcfisa_a|mcfhwdiv|mcfisa_b|mcfmac|mcfusp, mcf_ctrl, "cfv4", 0}, {mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "cfv4e", 0}, {0,0,NULL, 0} @@ -610,6 +627,13 @@ static const struct m68k_cpu m68k_cpus[] = {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "537x", 0}, {mcfisa_a|mcfisa_b|mcfhwdiv|mcfmac, mcf_ctrl, "5407",0}, + + {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54450", -1}, + {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54451", -1}, + {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54452", -1}, + {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54453", -1}, + {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54454", -1}, + {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54455", 0}, {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5470", -1}, {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5471", -1}, @@ -2206,6 +2230,8 @@ m68k_ip (char *instring) for (s = the_ins.args, opP = &the_ins.operands[0]; *s; s += 2, opP++) { + int have_disp = 0; + /* This switch is a doozy. Watch the first step; its a big one! */ switch (s[0]) @@ -2865,6 +2891,7 @@ m68k_ip (char *instring) case 'B': tmpreg = get_num (&opP->disp, 90); + switch (s[1]) { case 'B': @@ -2876,23 +2903,36 @@ m68k_ip (char *instring) break; case 'L': long_branch: - if (! HAVE_LONG_BRANCH (current_architecture)) - as_warn (_("Can't use long branches on 68000/68010/5200")); the_ins.opcode[0] |= 0xff; add_fix ('l', &opP->disp, 1, 0); addword (0); addword (0); break; - case 'g': - if (subs (&opP->disp)) /* We can't relax it. */ - goto long_branch; - + case 'g': /* Conditional branch */ + have_disp = HAVE_LONG_CALL (current_architecture); + goto var_branch; + + case 'b': /* Unconditional branch */ + have_disp = HAVE_LONG_BRANCH (current_architecture); + goto var_branch; + + case 's': /* Unconditional subroutine */ + have_disp = HAVE_LONG_CALL (current_architecture); + + var_branch: + if (subs (&opP->disp) /* We can't relax it. */ #ifdef OBJ_ELF - /* If the displacement needs pic relocation it cannot be - relaxed. */ - if (opP->disp.pic_reloc != pic_none) - goto long_branch; + /* If the displacement needs pic relocation it cannot be + relaxed. */ + || opP->disp.pic_reloc != pic_none #endif + || 0) + { + if (!have_disp) + as_warn (_("Can't use long branches on this architecture")); + goto long_branch; + } + /* This could either be a symbol, or an absolute address. If it's an absolute address, turn it into an absolute jump right here and keep it out of the @@ -2918,7 +2958,7 @@ m68k_ip (char *instring) /* Now we know it's going into the relaxer. Now figure out which mode. We try in this order of preference: long branch, absolute jump, byte/word branches only. */ - if (HAVE_LONG_BRANCH (current_architecture)) + if (have_disp) add_frag (adds (&opP->disp), SEXT (offs (&opP->disp)), TAB (BRANCHBWL, SZ_UNDEF)); @@ -2947,7 +2987,7 @@ m68k_ip (char *instring) jumps. */ if (((the_ins.opcode[0] & 0xf0f8) == 0x50c8) && (HAVE_LONG_BRANCH (current_architecture) - || (! flag_keep_pcrel))) + || ! flag_keep_pcrel)) { if (HAVE_LONG_BRANCH (current_architecture)) add_frag (adds (&opP->disp), @@ -7612,11 +7652,12 @@ m68k_elf_final_processing (void) { static const unsigned isa_features[][2] = { - {EF_M68K_CF_ISA_A_NODIV, mcfisa_a}, + {EF_M68K_CF_ISA_A_NODIV,mcfisa_a}, {EF_M68K_CF_ISA_A, mcfisa_a|mcfhwdiv}, - {EF_M68K_CF_ISA_A_PLUS,mcfisa_a|mcfisa_aa|mcfhwdiv|mcfusp}, + {EF_M68K_CF_ISA_A_PLUS, mcfisa_a|mcfisa_aa|mcfhwdiv|mcfusp}, {EF_M68K_CF_ISA_B_NOUSP,mcfisa_a|mcfisa_b|mcfhwdiv}, {EF_M68K_CF_ISA_B, mcfisa_a|mcfisa_b|mcfhwdiv|mcfusp}, + {EF_M68K_CF_ISA_C, mcfisa_a|mcfisa_c|mcfhwdiv|mcfusp}, {0,0}, }; static const unsigned mac_features[][2] = @@ -7629,7 +7670,7 @@ m68k_elf_final_processing (void) unsigned pattern; pattern = (current_architecture - & (mcfisa_a|mcfisa_aa|mcfisa_b|mcfhwdiv|mcfusp)); + & (mcfisa_a|mcfisa_aa|mcfisa_b|mcfisa_c|mcfhwdiv|mcfusp)); for (ix = 0; isa_features[ix][1]; ix++) { if (pattern == isa_features[ix][1]) diff --git a/gas/doc/c-m68k.texi b/gas/doc/c-m68k.texi index 0f8bb78..3176f94 100644 --- a/gas/doc/c-m68k.texi +++ b/gas/doc/c-m68k.texi @@ -45,7 +45,8 @@ architectures are recognized: @code{cpu32}, @code{isaa}, @code{isaaplus}, -@code{isab} and +@code{isab}, +@code{isac} and @code{cfv4e}. diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog index 4ba13fa..3eaea07 100644 --- a/gas/testsuite/ChangeLog +++ b/gas/testsuite/ChangeLog @@ -1,3 +1,13 @@ +2007-04-23 Nathan Sidwell + + * gas/m68k/br-isaa.s: New. + * gas/m68k/br-isaa.d: New. + * gas/m68k/br-isab.s: New. + * gas/m68k/br-isab.d: New. + * gas/m68k/br-isac.s: New. + * gas/m68k/br-isac.d: New. + * gas/m68k/all.exp: Adjust. + 2007-04-21 Richard Earnshaw * gas/arm/arch4t.d: Convert to unified syntax. diff --git a/gas/testsuite/gas/m68k/all.exp b/gas/testsuite/gas/m68k/all.exp index 62badbc..069d4af 100644 --- a/gas/testsuite/gas/m68k/all.exp +++ b/gas/testsuite/gas/m68k/all.exp @@ -52,6 +52,10 @@ if { [istarget m68*-*-*] || [istarget fido*-*-*] } then { run_dump_test arch-cpu-1 run_dump_test cpu32 + run_dump_test br-isaa + run_dump_test br-isab + run_dump_test br-isac + run_dump_test ctrl-1 run_dump_test ctrl-2 diff --git a/gas/testsuite/gas/m68k/br-isaa.d b/gas/testsuite/gas/m68k/br-isaa.d new file mode 100644 index 0000000..0b49dc2 --- /dev/null +++ b/gas/testsuite/gas/m68k/br-isaa.d @@ -0,0 +1,15 @@ +#name: br-isaa.d +#objdump: -d +#as: -march=isaa -pcrel + +.*: file format .* + +Disassembly of section .text: + +0+ : + 0: 4e71 nop + 2: 60fc bras 0 + 4: 6000 0000 braw 6 + 8: 61f6 bsrs 0 + a: 6100 0000 bsrw c + e: 4e71 nop diff --git a/gas/testsuite/gas/m68k/br-isaa.s b/gas/testsuite/gas/m68k/br-isaa.s new file mode 100644 index 0000000..d405338 --- /dev/null +++ b/gas/testsuite/gas/m68k/br-isaa.s @@ -0,0 +1,6 @@ +foo: nop + jbra foo + jbra bar + jbsr foo + jbsr bar + nop diff --git a/gas/testsuite/gas/m68k/br-isab.d b/gas/testsuite/gas/m68k/br-isab.d new file mode 100644 index 0000000..7ba48ff --- /dev/null +++ b/gas/testsuite/gas/m68k/br-isab.d @@ -0,0 +1,16 @@ +#name: br-isaa.d +#objdump: -d +#as: -march=isab -pcrel + +.*: file format .* + +Disassembly of section .text: + +0+ : + 0: 4e71 nop + 2: 61ff ffff fffc bsrl 0 + 8: 60f6 bras 0 + a: 60ff 0000 0000 bral c + 10: 61ee bsrs 0 + 12: 61ff 0000 0000 bsrl 14 + 18: 4e71 nop diff --git a/gas/testsuite/gas/m68k/br-isab.s b/gas/testsuite/gas/m68k/br-isab.s new file mode 100644 index 0000000..5db3c07 --- /dev/null +++ b/gas/testsuite/gas/m68k/br-isab.s @@ -0,0 +1,7 @@ +foo: nop + bsr.l foo + jbra foo + jbra bar + jbsr foo + jbsr bar + nop diff --git a/gas/testsuite/gas/m68k/br-isac.d b/gas/testsuite/gas/m68k/br-isac.d new file mode 100644 index 0000000..4a420ea --- /dev/null +++ b/gas/testsuite/gas/m68k/br-isac.d @@ -0,0 +1,16 @@ +#name: br-isaa.d +#objdump: -d +#as: -march=isac -pcrel + +.*: file format .* + +Disassembly of section .text: + +0+ : + 0: 4e71 nop + 2: 61ff ffff fffc bsrl 0 + 8: 60f6 bras 0 + a: 6000 0000 braw c + e: 61f0 bsrs 0 + 10: 61ff 0000 0000 bsrl 12 + 16: 4e71 nop diff --git a/gas/testsuite/gas/m68k/br-isac.s b/gas/testsuite/gas/m68k/br-isac.s new file mode 100644 index 0000000..5db3c07 --- /dev/null +++ b/gas/testsuite/gas/m68k/br-isac.s @@ -0,0 +1,7 @@ +foo: nop + bsr.l foo + jbra foo + jbra bar + jbsr foo + jbsr bar + nop diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog index 55999e4..0c304a7 100644 --- a/include/opcode/ChangeLog +++ b/include/opcode/ChangeLog @@ -1,3 +1,8 @@ +2007-04-23 Nathan Sidwell + + * m68k.h (mcfisa_c): New. + (mcfusp, mcf_mask): Adjust. + 2007-04-20 Alan Modra * ppc.h (struct powerpc_operand): Replace "bits" with "bitm". diff --git a/include/opcode/m68k.h b/include/opcode/m68k.h index f87a7a3..60bfb3a 100644 --- a/include/opcode/m68k.h +++ b/include/opcode/m68k.h @@ -41,9 +41,10 @@ #define mcfisa_a 0x4000 /* ColdFire ISA_A. */ #define mcfisa_aa 0x8000 /* ColdFire ISA_A+. */ -#define mcfisa_b 0x10000 /* ColdFire ISA_B. */ -#define mcfusp 0x20000 /* ColdFire USP instructions. */ -#define mcf_mask 0x3e400 +#define mcfisa_b 0x10000 /* ColdFire ISA_B. */ +#define mcfisa_c 0x20000 /* ColdFire ISA_C. */ +#define mcfusp 0x40000 /* ColdFire USP instructions. */ +#define mcf_mask 0x7e400 /* Handy aliases. */ #define m68040up (m68040 | m68060) diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 119325b..bff2cde 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,7 @@ +2007-04-23 Nathan Sidwell + + * m68k-opc.c: Mark mcfisa_c instructions. + 2007-04-21 Richard Earnshaw * arm-dis.c (arm_opcodes): Disassemble to unified syntax. diff --git a/opcodes/m68k-opc.c b/opcodes/m68k-opc.c index c3948cf..b0f1885 100644 --- a/opcodes/m68k-opc.c +++ b/opcodes/m68k-opc.c @@ -131,20 +131,20 @@ const struct m68k_opcode m68k_opcodes[] = {"bgtw", 2, one(0067000), one(0177777), "BW", m68000up | mcfisa_a }, {"blew", 2, one(0067400), one(0177777), "BW", m68000up | mcfisa_a }, -{"bhil", 2, one(0061377), one(0177777), "BL", m68020up | cpu32 | fido_a | mcfisa_b}, -{"blsl", 2, one(0061777), one(0177777), "BL", m68020up | cpu32 | fido_a | mcfisa_b}, -{"bccl", 2, one(0062377), one(0177777), "BL", m68020up | cpu32 | fido_a | mcfisa_b}, -{"bcsl", 2, one(0062777), one(0177777), "BL", m68020up | cpu32 | fido_a | mcfisa_b}, -{"bnel", 2, one(0063377), one(0177777), "BL", m68020up | cpu32 | fido_a | mcfisa_b}, -{"beql", 2, one(0063777), one(0177777), "BL", m68020up | cpu32 | fido_a | mcfisa_b}, -{"bvcl", 2, one(0064377), one(0177777), "BL", m68020up | cpu32 | fido_a | mcfisa_b}, -{"bvsl", 2, one(0064777), one(0177777), "BL", m68020up | cpu32 | fido_a | mcfisa_b}, -{"bpll", 2, one(0065377), one(0177777), "BL", m68020up | cpu32 | fido_a | mcfisa_b}, -{"bmil", 2, one(0065777), one(0177777), "BL", m68020up | cpu32 | fido_a | mcfisa_b}, -{"bgel", 2, one(0066377), one(0177777), "BL", m68020up | cpu32 | fido_a | mcfisa_b}, -{"bltl", 2, one(0066777), one(0177777), "BL", m68020up | cpu32 | fido_a | mcfisa_b}, -{"bgtl", 2, one(0067377), one(0177777), "BL", m68020up | cpu32 | fido_a | mcfisa_b}, -{"blel", 2, one(0067777), one(0177777), "BL", m68020up | cpu32 | fido_a | mcfisa_b}, +{"bhil", 2, one(0061377), one(0177777), "BL", m68020up | cpu32 | fido_a | mcfisa_b | mcfisa_c}, +{"blsl", 2, one(0061777), one(0177777), "BL", m68020up | cpu32 | fido_a | mcfisa_b | mcfisa_c}, +{"bccl", 2, one(0062377), one(0177777), "BL", m68020up | cpu32 | fido_a | mcfisa_b | mcfisa_c}, +{"bcsl", 2, one(0062777), one(0177777), "BL", m68020up | cpu32 | fido_a | mcfisa_b | mcfisa_c}, +{"bnel", 2, one(0063377), one(0177777), "BL", m68020up | cpu32 | fido_a | mcfisa_b | mcfisa_c}, +{"beql", 2, one(0063777), one(0177777), "BL", m68020up | cpu32 | fido_a | mcfisa_b | mcfisa_c}, +{"bvcl", 2, one(0064377), one(0177777), "BL", m68020up | cpu32 | fido_a | mcfisa_b | mcfisa_c}, +{"bvsl", 2, one(0064777), one(0177777), "BL", m68020up | cpu32 | fido_a | mcfisa_b | mcfisa_c}, +{"bpll", 2, one(0065377), one(0177777), "BL", m68020up | cpu32 | fido_a | mcfisa_b | mcfisa_c}, +{"bmil", 2, one(0065777), one(0177777), "BL", m68020up | cpu32 | fido_a | mcfisa_b | mcfisa_c}, +{"bgel", 2, one(0066377), one(0177777), "BL", m68020up | cpu32 | fido_a | mcfisa_b | mcfisa_c}, +{"bltl", 2, one(0066777), one(0177777), "BL", m68020up | cpu32 | fido_a | mcfisa_b | mcfisa_c}, +{"bgtl", 2, one(0067377), one(0177777), "BL", m68020up | cpu32 | fido_a | mcfisa_b | mcfisa_c}, +{"blel", 2, one(0067777), one(0177777), "BL", m68020up | cpu32 | fido_a | mcfisa_b | mcfisa_c}, {"bhis", 2, one(0061000), one(0177400), "BB", m68000up | mcfisa_a }, {"blss", 2, one(0061400), one(0177400), "BB", m68000up | mcfisa_a }, @@ -195,7 +195,7 @@ const struct m68k_opcode m68k_opcodes[] = {"bgnd", 2, one(0045372), one(0177777), "", cpu32 | fido_a }, -{"bitrev", 2, one(0000300), one(0177770), "Ds", mcfisa_aa}, +{"bitrev", 2, one(0000300), one(0177770), "Ds", mcfisa_aa | mcfisa_c}, {"bkpt", 2, one(0044110), one(0177770), "ts", m68010up }, @@ -209,14 +209,14 @@ const struct m68k_opcode m68k_opcodes[] = {"bset", 4, one(0004300), one(0177700), "#bqs", mcfisa_a }, {"bsrw", 2, one(0060400), one(0177777), "BW", m68000up | mcfisa_a }, -{"bsrl", 2, one(0060777), one(0177777), "BL", m68020up | cpu32 | fido_a | mcfisa_b}, +{"bsrl", 2, one(0060777), one(0177777), "BL", m68020up | cpu32 | fido_a | mcfisa_b | mcfisa_c}, {"bsrs", 2, one(0060400), one(0177400), "BB", m68000up | mcfisa_a }, {"btst", 2, one(0000400), one(0170700), "Dd;b", m68000up | mcfisa_a }, {"btst", 4, one(0004000), one(0177700), "#b@s", m68000up }, {"btst", 4, one(0004000), one(0177700), "#bqs", mcfisa_a }, -{"byterev", 2, one(0001300), one(0177770), "Ds", mcfisa_aa}, +{"byterev", 2, one(0001300), one(0177770), "Ds", mcfisa_aa | mcfisa_c}, {"callm", 4, one(0003300), one(0177700), "#b!s", m68020 }, @@ -264,9 +264,9 @@ const struct m68k_opcode m68k_opcodes[] = {"cmpal", 2, one(0130700), one(0170700), "*lAd", m68000up | mcfisa_a }, {"cmpib", 4, one(0006000), one(0177700), "#b@s", m68000up }, -{"cmpib", 4, one(0006000), one(0177700), "#bDs", mcfisa_b }, +{"cmpib", 4, one(0006000), one(0177700), "#bDs", mcfisa_b | mcfisa_c }, {"cmpiw", 4, one(0006100), one(0177700), "#w@s", m68000up }, -{"cmpiw", 4, one(0006100), one(0177700), "#wDs", mcfisa_b }, +{"cmpiw", 4, one(0006100), one(0177700), "#wDs", mcfisa_b | mcfisa_c }, {"cmpil", 6, one(0006200), one(0177700), "#l@s", m68000up }, {"cmpil", 6, one(0006200), one(0177700), "#lDs", mcfisa_a }, @@ -276,15 +276,15 @@ const struct m68k_opcode m68k_opcodes[] = /* The cmp opcode can generate the cmpa, cmpm, and cmpi instructions. */ {"cmpb", 4, one(0006000), one(0177700), "#b@s", m68000up }, -{"cmpb", 4, one(0006000), one(0177700), "#bDs", mcfisa_b }, +{"cmpb", 4, one(0006000), one(0177700), "#bDs", mcfisa_b | mcfisa_c }, {"cmpb", 2, one(0130410), one(0170770), "+s+d", m68000up }, {"cmpb", 2, one(0130000), one(0170700), ";bDd", m68000up }, -{"cmpb", 2, one(0130000), one(0170700), "*bDd", mcfisa_b }, +{"cmpb", 2, one(0130000), one(0170700), "*bDd", mcfisa_b | mcfisa_c }, {"cmpw", 2, one(0130300), one(0170700), "*wAd", m68000up }, {"cmpw", 4, one(0006100), one(0177700), "#w@s", m68000up }, -{"cmpw", 4, one(0006100), one(0177700), "#wDs", mcfisa_b }, +{"cmpw", 4, one(0006100), one(0177700), "#wDs", mcfisa_b | mcfisa_c }, {"cmpw", 2, one(0130510), one(0170770), "+s+d", m68000up }, -{"cmpw", 2, one(0130100), one(0170700), "*wDd", m68000up | mcfisa_b }, +{"cmpw", 2, one(0130100), one(0170700), "*wDd", m68000up | mcfisa_b | mcfisa_c }, {"cmpl", 2, one(0130700), one(0170700), "*lAd", m68000up | mcfisa_a }, {"cmpl", 6, one(0006200), one(0177700), "#l@s", m68000up }, {"cmpl", 6, one(0006200), one(0177700), "#lDs", mcfisa_a }, @@ -360,7 +360,7 @@ const struct m68k_opcode m68k_opcodes[] = {"extl", 2, one(0044300), one(0177770), "Ds", m68000up|mcfisa_a }, {"extbl", 2, one(0044700), one(0177770), "Ds", m68020up | cpu32 | fido_a | mcfisa_a }, -{"ff1", 2, one(0002300), one(0177770), "Ds", mcfisa_aa}, +{"ff1", 2, one(0002300), one(0177770), "Ds", mcfisa_aa | mcfisa_c}, /* float stuff starts here */ @@ -1423,16 +1423,16 @@ const struct m68k_opcode m68k_opcodes[] = {"halt", 2, one(0045310), one(0177777), "", m68060 | mcfisa_a }, {"illegal", 2, one(0045374), one(0177777), "", m68000up | mcfisa_a }, -{"intouch", 2, one(0xf428), one(0xfff8), "As", mcfisa_b }, +{"intouch", 2, one(0xf428), one(0xfff8), "As", mcfisa_b | mcfisa_c }, {"jmp", 2, one(0047300), one(0177700), "!s", m68000up | mcfisa_a }, -{"jra", 2, one(0060000), one(0177400), "Bg", m68000up | mcfisa_a }, +{"jra", 2, one(0060000), one(0177400), "Bb", m68000up | mcfisa_a }, {"jra", 2, one(0047300), one(0177700), "!s", m68000up | mcfisa_a }, {"jsr", 2, one(0047200), one(0177700), "!s", m68000up | mcfisa_a }, -{"jbsr", 2, one(0060400), one(0177400), "Bg", m68000up | mcfisa_a }, +{"jbsr", 2, one(0060400), one(0177400), "Bs", m68000up | mcfisa_a }, {"jbsr", 2, one(0047200), one(0177700), "!s", m68000up | mcfisa_a }, {"lea", 2, one(0040700), one(0170700), "!sAd", m68000up | mcfisa_a }, @@ -1553,13 +1553,13 @@ const struct m68k_opcode m68k_opcodes[] = {"moveb", 2, one(0010200), one(0170700), "obad", mcfisa_a }, {"moveb", 2, one(0010300), one(0170700), "ob+d", mcfisa_a }, {"moveb", 2, one(0010400), one(0170700), "ob-d", mcfisa_a }, -{"moveb", 2, one(0010000), one(0170000), "obnd", mcfisa_b }, +{"moveb", 2, one(0010000), one(0170000), "obnd", mcfisa_b | mcfisa_c }, {"movew", 2, one(0030000), one(0170000), "*w%d", m68000up }, {"movew", 2, one(0030000), one(0170000), "ms%d", mcfisa_a }, {"movew", 2, one(0030000), one(0170000), "nspd", mcfisa_a }, {"movew", 2, one(0030000), one(0170000), "owmd", mcfisa_a }, -{"movew", 2, one(0030000), one(0170000), "ownd", mcfisa_b }, +{"movew", 2, one(0030000), one(0170000), "ownd", mcfisa_b | mcfisa_c }, {"movew", 2, one(0040300), one(0177700), "Ss$s", m68000up }, {"movew", 2, one(0040300), one(0177770), "SsDs", mcfisa_a }, {"movew", 2, one(0041300), one(0177700), "Cs$s", m68010up }, @@ -1576,7 +1576,7 @@ const struct m68k_opcode m68k_opcodes[] = {"movel", 2, one(0020000), one(0170000), "ms%d", mcfisa_a }, {"movel", 2, one(0020000), one(0170000), "nspd", mcfisa_a }, {"movel", 2, one(0020000), one(0170000), "olmd", mcfisa_a }, -{"movel", 2, one(0020000), one(0170000), "olnd", mcfisa_b }, +{"movel", 2, one(0020000), one(0170000), "olnd", mcfisa_b | mcfisa_c }, {"movel", 2, one(0047140), one(0177770), "AsUd", m68000up | mcfusp }, {"movel", 2, one(0047150), one(0177770), "UdAs", m68000up | mcfusp }, {"movel", 2, one(0120600), one(0177760), "EsRs", mcfmac }, @@ -1609,7 +1609,7 @@ const struct m68k_opcode m68k_opcodes[] = {"move", 2, one(0030000), one(0170000), "ms%d", mcfisa_a }, {"move", 2, one(0030000), one(0170000), "nspd", mcfisa_a }, {"move", 2, one(0030000), one(0170000), "owmd", mcfisa_a }, -{"move", 2, one(0030000), one(0170000), "ownd", mcfisa_b }, +{"move", 2, one(0030000), one(0170000), "ownd", mcfisa_b | mcfisa_c }, {"move", 2, one(0040300), one(0177700), "Ss$s", m68000up }, {"move", 2, one(0040300), one(0177770), "SsDs", mcfisa_a }, {"move", 2, one(0041300), one(0177700), "Cs$s", m68010up }, @@ -1624,11 +1624,11 @@ const struct m68k_opcode m68k_opcodes[] = {"move", 2, one(0047140), one(0177770), "AsUd", m68000up }, {"move", 2, one(0047150), one(0177770), "UdAs", m68000up }, -{"mov3ql", 2, one(0120500), one(0170700), "xd%s", mcfisa_b }, -{"mvsb", 2, one(0070400), one(0170700), "*bDd", mcfisa_b }, -{"mvsw", 2, one(0070500), one(0170700), "*wDd", mcfisa_b }, -{"mvzb", 2, one(0070600), one(0170700), "*bDd", mcfisa_b }, -{"mvzw", 2, one(0070700), one(0170700), "*wDd", mcfisa_b }, +{"mov3ql", 2, one(0120500), one(0170700), "xd%s", mcfisa_b | mcfisa_c }, +{"mvsb", 2, one(0070400), one(0170700), "*bDd", mcfisa_b | mcfisa_c }, +{"mvsw", 2, one(0070500), one(0170700), "*wDd", mcfisa_b | mcfisa_c }, +{"mvzb", 2, one(0070600), one(0170700), "*bDd", mcfisa_b | mcfisa_c }, +{"mvzw", 2, one(0070700), one(0170700), "*wDd", mcfisa_b | mcfisa_c }, {"movesb", 4, two(0007000, 0), two(0177700, 07777), "~sR1", m68010up }, {"movesb", 4, two(0007000, 04000), two(0177700, 07777), "R1~s", m68010up }, @@ -1993,7 +1993,7 @@ const struct m68k_opcode m68k_opcodes[] = {"rts", 2, one(0047165), one(0177777), "", m68000up | mcfisa_a }, -{"satsl", 2, one(0046200), one(0177770), "Ds", mcfisa_b }, +{"satsl", 2, one(0046200), one(0177770), "Ds", mcfisa_b | mcfisa_c }, {"sbcd", 2, one(0100400), one(0170770), "DsDd", m68000up }, {"sbcd", 2, one(0100410), one(0170770), "-s-d", m68000up }, @@ -2142,7 +2142,7 @@ const struct m68k_opcode m68k_opcodes[] = {"swbeg", 4, one(0045374), one(0177777), "#w", m68000up | mcfisa_a }, {"swbegl", 6, one(0045375), one(0177777), "#l", m68000up | mcfisa_a }, -{"tas", 2, one(0045300), one(0177700), "$s", m68000up | mcfisa_b}, +{"tas", 2, one(0045300), one(0177700), "$s", m68000up | mcfisa_b | mcfisa_c}, #define TBL1(name,insn_size,signed,round,size) \ {name, insn_size, two(0174000, (signed<<11)|(!round<<10)|(size<<6)|0000400), \