From: Kristian H. Kristensen <hoegsberg@gmail.com>
Date: Tue, 29 Nov 2016 01:46:05 +0000 (-0800)
Subject: intel/genxml: Use enum 3D_Logic_Op_Function where applicable
X-Git-Tag: upstream/17.1.0~4203
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=99e573b4e0aab912f0c6b663f72b17617a4d4529;p=platform%2Fupstream%2Fmesa.git

intel/genxml: Use enum 3D_Logic_Op_Function where applicable

Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
---

diff --git a/src/intel/genxml/gen6.xml b/src/intel/genxml/gen6.xml
index de626a7..575ba86 100644
--- a/src/intel/genxml/gen6.xml
+++ b/src/intel/genxml/gen6.xml
@@ -86,6 +86,25 @@
     <value name="INVERT" value="7"/>
   </enum>
 
+  <enum name="3D_Logic_Op_Function" prefix="LOGICOP">
+    <value name="CLEAR" value="0"/>
+    <value name="NOR" value="1"/>
+    <value name="AND_INVERTED" value="2"/>
+    <value name="COPY_INVERTED" value="3"/>
+    <value name="AND_REVERSE" value="4"/>
+    <value name="INVERT" value="5"/>
+    <value name="XOR" value="6"/>
+    <value name="NAND" value="7"/>
+    <value name="AND" value="8"/>
+    <value name="EQUIV" value="9"/>
+    <value name="NOOP" value="10"/>
+    <value name="OR_INVERTED" value="11"/>
+    <value name="COPY" value="12"/>
+    <value name="OR_REVERSE" value="13"/>
+    <value name="OR" value="14"/>
+    <value name="SET" value="15"/>
+  </enum>
+
   <enum name="SURFACE_FORMAT" prefix="SF">
     <value name="R32G32B32A32_FLOAT" value="0"/>
     <value name="R32G32B32A32_SINT" value="1"/>
@@ -417,24 +436,7 @@
     <field name="Write Disable Green" start="57" end="57" type="bool"/>
     <field name="Write Disable Blue" start="56" end="56" type="bool"/>
     <field name="Logic Op Enable" start="54" end="54" type="bool"/>
-    <field name="Logic Op Function" start="50" end="53" type="uint">
-      <value name="LOGICOP_CLEAR" value="0"/>
-      <value name="LOGICOP_NOR" value="1"/>
-      <value name="LOGICOP_AND_INVERTED" value="2"/>
-      <value name="LOGICOP_COPY_INVERTED" value="3"/>
-      <value name="LOGICOP_AND_REVERSE" value="4"/>
-      <value name="LOGICOP_INVERT" value="5"/>
-      <value name="LOGICOP_XOR" value="6"/>
-      <value name="LOGICOP_NAND" value="7"/>
-      <value name="LOGICOP_AND" value="8"/>
-      <value name="LOGICOP_EQUIV" value="9"/>
-      <value name="LOGICOP_NOOP" value="10"/>
-      <value name="LOGICOP_OR_INVERTED" value="11"/>
-      <value name="LOGICOP_COPY" value="12"/>
-      <value name="LOGICOP_OR_REVERSE" value="13"/>
-      <value name="LOGICOP_OR" value="14"/>
-      <value name="LOGICOP_SET" value="15"/>
-    </field>
+    <field name="Logic Op Function" start="50" end="53" type="3D_Logic_Op_Function"/>
     <field name="Alpha Test Enable" start="48" end="48" type="bool"/>
     <field name="Alpha Test Function" start="45" end="47" type="3D_Compare_Function"/>
     <field name="Color Dither Enable" start="44" end="44" type="bool"/>
diff --git a/src/intel/genxml/gen7.xml b/src/intel/genxml/gen7.xml
index 2c269d4..6bde403 100644
--- a/src/intel/genxml/gen7.xml
+++ b/src/intel/genxml/gen7.xml
@@ -118,6 +118,25 @@
     <value name="GEQUAL" value="7"/>
   </enum>
 
+  <enum name="3D_Logic_Op_Function" prefix="LOGICOP">
+    <value name="CLEAR" value="0"/>
+    <value name="NOR" value="1"/>
+    <value name="AND_INVERTED" value="2"/>
+    <value name="COPY_INVERTED" value="3"/>
+    <value name="AND_REVERSE" value="4"/>
+    <value name="INVERT" value="5"/>
+    <value name="XOR" value="6"/>
+    <value name="NAND" value="7"/>
+    <value name="AND" value="8"/>
+    <value name="EQUIV" value="9"/>
+    <value name="NOOP" value="10"/>
+    <value name="OR_INVERTED" value="11"/>
+    <value name="COPY" value="12"/>
+    <value name="OR_REVERSE" value="13"/>
+    <value name="OR" value="14"/>
+    <value name="SET" value="15"/>
+  </enum>
+
   <enum name="SURFACE_FORMAT" prefix="SF">
     <value name="R32G32B32A32_FLOAT" value="0"/>
     <value name="R32G32B32A32_SINT" value="1"/>
@@ -472,24 +491,7 @@
     <field name="Write Disable Green" start="57" end="57" type="bool"/>
     <field name="Write Disable Blue" start="56" end="56" type="bool"/>
     <field name="Logic Op Enable" start="54" end="54" type="bool"/>
-    <field name="Logic Op Function" start="50" end="53" type="uint">
-      <value name="LOGICOP_CLEAR" value="0"/>
-      <value name="LOGICOP_NOR" value="1"/>
-      <value name="LOGICOP_AND_INVERTED" value="2"/>
-      <value name="LOGICOP_COPY_INVERTED" value="3"/>
-      <value name="LOGICOP_AND_REVERSE" value="4"/>
-      <value name="LOGICOP_INVERT" value="5"/>
-      <value name="LOGICOP_XOR" value="6"/>
-      <value name="LOGICOP_NAND" value="7"/>
-      <value name="LOGICOP_AND" value="8"/>
-      <value name="LOGICOP_EQUIV" value="9"/>
-      <value name="LOGICOP_NOOP" value="10"/>
-      <value name="LOGICOP_OR_INVERTED" value="11"/>
-      <value name="LOGICOP_COPY" value="12"/>
-      <value name="LOGICOP_OR_REVERSE" value="13"/>
-      <value name="LOGICOP_OR" value="14"/>
-      <value name="LOGICOP_SET" value="15"/>
-    </field>
+    <field name="Logic Op Function" start="50" end="53" type="3D_Logic_Op_Function"/>
     <field name="Alpha Test Enable" start="48" end="48" type="bool"/>
     <field name="Alpha Test Function" start="45" end="47" type="3D_Compare_Function"/>
     <field name="Color Dither Enable" start="44" end="44" type="bool"/>
diff --git a/src/intel/genxml/gen75.xml b/src/intel/genxml/gen75.xml
index 0104236..2ff75bd 100644
--- a/src/intel/genxml/gen75.xml
+++ b/src/intel/genxml/gen75.xml
@@ -118,6 +118,25 @@
     <value name="GEQUAL" value="7"/>
   </enum>
 
+  <enum name="3D_Logic_Op_Function" prefix="LOGICOP">
+    <value name="CLEAR" value="0"/>
+    <value name="NOR" value="1"/>
+    <value name="AND_INVERTED" value="2"/>
+    <value name="COPY_INVERTED" value="3"/>
+    <value name="AND_REVERSE" value="4"/>
+    <value name="INVERT" value="5"/>
+    <value name="XOR" value="6"/>
+    <value name="NAND" value="7"/>
+    <value name="AND" value="8"/>
+    <value name="EQUIV" value="9"/>
+    <value name="NOOP" value="10"/>
+    <value name="OR_INVERTED" value="11"/>
+    <value name="COPY" value="12"/>
+    <value name="OR_REVERSE" value="13"/>
+    <value name="OR" value="14"/>
+    <value name="SET" value="15"/>
+  </enum>
+
   <enum name="SURFACE_FORMAT" prefix="SF">
     <value name="R32G32B32A32_FLOAT" value="0"/>
     <value name="R32G32B32A32_SINT" value="1"/>
@@ -482,24 +501,7 @@
     <field name="Write Disable Green" start="57" end="57" type="bool"/>
     <field name="Write Disable Blue" start="56" end="56" type="bool"/>
     <field name="Logic Op Enable" start="54" end="54" type="bool"/>
-    <field name="Logic Op Function" start="50" end="53" type="uint">
-      <value name="LOGICOP_CLEAR" value="0"/>
-      <value name="LOGICOP_NOR" value="1"/>
-      <value name="LOGICOP_AND_INVERTED" value="2"/>
-      <value name="LOGICOP_COPY_INVERTED" value="3"/>
-      <value name="LOGICOP_AND_REVERSE" value="4"/>
-      <value name="LOGICOP_INVERT" value="5"/>
-      <value name="LOGICOP_XOR" value="6"/>
-      <value name="LOGICOP_NAND" value="7"/>
-      <value name="LOGICOP_AND" value="8"/>
-      <value name="LOGICOP_EQUIV" value="9"/>
-      <value name="LOGICOP_NOOP" value="10"/>
-      <value name="LOGICOP_OR_INVERTED" value="11"/>
-      <value name="LOGICOP_COPY" value="12"/>
-      <value name="LOGICOP_OR_REVERSE" value="13"/>
-      <value name="LOGICOP_OR" value="14"/>
-      <value name="LOGICOP_SET" value="15"/>
-    </field>
+    <field name="Logic Op Function" start="50" end="53" type="3D_Logic_Op_Function"/>
     <field name="Alpha Test Enable" start="48" end="48" type="bool"/>
     <field name="Alpha Test Function" start="45" end="47" type="3D_Compare_Function"/>
     <field name="Color Dither Enable" start="44" end="44" type="bool"/>
diff --git a/src/intel/genxml/gen8.xml b/src/intel/genxml/gen8.xml
index f9c1ab3..7df479c 100644
--- a/src/intel/genxml/gen8.xml
+++ b/src/intel/genxml/gen8.xml
@@ -523,7 +523,7 @@
 
   <struct name="BLEND_STATE_ENTRY" length="2">
     <field name="Logic Op Enable" start="63" end="63" type="bool"/>
-    <field name="Logic Op Function" start="59" end="62" type="uint"/>
+    <field name="Logic Op Function" start="59" end="62" type="3D_Logic_Op_Function"/>
     <field name="Pre-Blend Source Only Clamp Enable" start="36" end="36" type="bool"/>
     <field name="Color Clamp Range" start="34" end="35" type="uint">
       <value name="COLORCLAMP_UNORM" value="0"/>
diff --git a/src/intel/genxml/gen9.xml b/src/intel/genxml/gen9.xml
index 5ba6ba1..ec85494 100644
--- a/src/intel/genxml/gen9.xml
+++ b/src/intel/genxml/gen9.xml
@@ -532,7 +532,7 @@
 
   <struct name="BLEND_STATE_ENTRY" length="2">
     <field name="Logic Op Enable" start="63" end="63" type="bool"/>
-    <field name="Logic Op Function" start="59" end="62" type="uint"/>
+    <field name="Logic Op Function" start="59" end="62" type="3D_Logic_Op_Function"/>
     <field name="Pre-Blend Source Only Clamp Enable" start="36" end="36" type="bool"/>
     <field name="Color Clamp Range" start="34" end="35" type="uint">
       <value name="COLORCLAMP_UNORM" value="0"/>