From: H.J. Lu <hjl.tools@gmail.com>
Date: Sat, 2 Mar 2013 01:57:48 +0000 (+0000)
Subject: Add RegRex64 to riz
X-Git-Tag: gdb_7_6-2013-03-12-branchpoint~127
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=99dce992c484775ffdb25a2c22187757cc5165ec;p=external%2Fbinutils.git

Add RegRex64 to riz

	* i386-reg.tbl (riz): Add RegRex64.
	* i386-tbl.h: Regenerated.
---

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 374bf40..8ec6e82 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,8 @@
+2013-03-01  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* i386-reg.tbl (riz): Add RegRex64.
+	* i386-tbl.h: Regenerated.
+
 2013-02-28  Yufeng Zhang  <yufeng.zhang@arm.com>
 
 	* aarch64-tbl.h (QL_I3SAMEW, QL_I3WWX): New macros.
diff --git a/opcodes/i386-reg.tbl b/opcodes/i386-reg.tbl
index 8c5b5d1..8eed65b 100644
--- a/opcodes/i386-reg.tbl
+++ b/opcodes/i386-reg.tbl
@@ -211,8 +211,8 @@ rip, BaseIndex, RegRex64, RegRip, Dw2Inval, 16
 eip, BaseIndex, RegRex64, RegEip, 8, Dw2Inval
 // No type will make these registers rejected for all purposes except
 // for addressing.
+riz, BaseIndex, RegRex64, RegRiz, Dw2Inval, Dw2Inval
 eiz, BaseIndex, 0, RegEiz, Dw2Inval, Dw2Inval
-riz, BaseIndex, 0, RegRiz, Dw2Inval, Dw2Inval
 // fp regs.
 st(0), FloatReg|FloatAcc, 0, 0, 11, 33
 st(1), FloatReg, 0, 1, 12, 34
diff --git a/opcodes/i386-tbl.h b/opcodes/i386-tbl.h
index cab6b07..f9a3882 100644
--- a/opcodes/i386-tbl.h
+++ b/opcodes/i386-tbl.h
@@ -40246,16 +40246,16 @@ const reg_entry i386_regtab[] =
 	0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
 	0, 0, 0, 0, 0, 0 } },
     RegRex64, RegEip, { 8, Dw2Inval } },
-  { "eiz",
+  { "riz",
     { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
 	0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
 	0, 0, 0, 0, 0, 0 } },
-    0, RegEiz, { Dw2Inval, Dw2Inval } },
-  { "riz",
+    RegRex64, RegRiz, { Dw2Inval, Dw2Inval } },
+  { "eiz",
     { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
 	0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
 	0, 0, 0, 0, 0, 0 } },
-    0, RegRiz, { Dw2Inval, Dw2Inval } },
+    0, RegEiz, { Dw2Inval, Dw2Inval } },
   { "st(0)",
     { { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
 	0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,