From: Frank van Maarseveen Date: Fri, 9 Sep 2005 20:01:46 +0000 (-0700) Subject: [PATCH] ppc32: Correct an instruction in the boot code X-Git-Tag: v3.12-rc1~42018 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=99cc2192132ab28c495d015ed2e95dc29e2a27ad;p=kernel%2Fkernel-generic.git [PATCH] ppc32: Correct an instruction in the boot code In the flush and invalidate bootcode on PPC4xx we were accidentally using the wrong instruction. Use cmplw, which reads from a register like we want. Signed-off-by: Tom Rini Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- diff --git a/arch/ppc/boot/common/util.S b/arch/ppc/boot/common/util.S index 47e6414..c96c9f8 100644 --- a/arch/ppc/boot/common/util.S +++ b/arch/ppc/boot/common/util.S @@ -252,7 +252,7 @@ _GLOBAL(flush_instruction_cache) 1: dcbf r0,r3 # Flush the data cache icbi r0,r3 # Invalidate the instruction cache addi r3,r3,0x10 # Increment by one cache line - cmplwi cr0,r3,r4 # Are we at the end yet? + cmplw cr0,r3,r4 # Are we at the end yet? blt 1b # No, keep flushing and invalidating #else /* Enable, invalidate and then disable the L1 icache/dcache. */