From: Gabriel Ravier Date: Fri, 30 Sep 2022 15:00:56 +0000 (+0200) Subject: [BOLT] Fixed some typos X-Git-Tag: upstream/17.0.6~31971 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=9966b3e7281e8e283caf75fe061ed3037837758f;p=platform%2Fupstream%2Fllvm.git [BOLT] Fixed some typos I went over the output of the following mess of a command: `(ulimit -m 2000000; ulimit -v 2000000; git ls-files -z | parallel --xargs -0 cat | aspell list --mode=none --ignore-case | grep -E '^[A-Za-z][a-z]*$' | sort | uniq -c | sort -n | grep -vE '.{25}' | aspell pipe -W3 | grep : | cut -d' ' -f2 | less)` and proceeded to spend a few days looking at it to find probable typos and fixed a few hundred of them in all of the llvm project (note, the ones I found are not anywhere near all of them, but it seems like a good start). Reviewed By: Amir, maksfb Differential Revision: https://reviews.llvm.org/D130824 --- diff --git a/bolt/include/bolt/Core/DebugData.h b/bolt/include/bolt/Core/DebugData.h index 347fd294b..59b6c84 100644 --- a/bolt/include/bolt/Core/DebugData.h +++ b/bolt/include/bolt/Core/DebugData.h @@ -330,8 +330,8 @@ public: protected: class AddressForDWOCU { public: - AddressToIndexMap::iterator find(uint64_t Adddress) { - return AddressToIndex.find(Adddress); + AddressToIndexMap::iterator find(uint64_t Address) { + return AddressToIndex.find(Address); } AddressToIndexMap::iterator end() { return AddressToIndex.end(); } AddressToIndexMap::iterator begin() { return AddressToIndex.begin(); } diff --git a/bolt/include/bolt/Core/MCPlusBuilder.h b/bolt/include/bolt/Core/MCPlusBuilder.h index 7b3c448..9e2f5cd 100644 --- a/bolt/include/bolt/Core/MCPlusBuilder.h +++ b/bolt/include/bolt/Core/MCPlusBuilder.h @@ -1431,7 +1431,7 @@ public: return false; } - /// Store \p Target absolute adddress to \p RegName + /// Store \p Target absolute address to \p RegName virtual InstructionListType materializeAddress(const MCSymbol *Target, MCContext *Ctx, MCPhysReg RegName, diff --git a/bolt/lib/Passes/BinaryPasses.cpp b/bolt/lib/Passes/BinaryPasses.cpp index f240b1a..8afd619 100644 --- a/bolt/lib/Passes/BinaryPasses.cpp +++ b/bolt/lib/Passes/BinaryPasses.cpp @@ -894,7 +894,7 @@ uint64_t SimplifyConditionalTailCalls::fixTailCalls(BinaryFunction &BF) { // Annotate it, so "isCall" returns true for this jcc MIB->setConditionalTailCall(*CondBranch); - // Add info abount the conditional tail call frequency, otherwise this + // Add info about the conditional tail call frequency, otherwise this // info will be lost when we delete the associated BranchInfo entry auto &CTCAnnotation = MIB->getOrCreateAnnotationAs(*CondBranch, "CTCTakenCount"); diff --git a/bolt/lib/Passes/IndirectCallPromotion.cpp b/bolt/lib/Passes/IndirectCallPromotion.cpp index e4b577a..af07237 100644 --- a/bolt/lib/Passes/IndirectCallPromotion.cpp +++ b/bolt/lib/Passes/IndirectCallPromotion.cpp @@ -416,15 +416,15 @@ IndirectCallPromotion::maybeGetHotJumpTableTargets(BinaryBasicBlock &BB, ++TotalIndexBasedCandidates; - auto ErrorOrMemAccesssProfile = + auto ErrorOrMemAccessProfile = BC.MIB->tryGetAnnotationAs(*MemLocInstr, "MemoryAccessProfile"); - if (!ErrorOrMemAccesssProfile) { + if (!ErrorOrMemAccessProfile) { DEBUG_VERBOSE(1, dbgs() << "BOLT-INFO: ICP no memory profiling data found\n"); return JumpTableInfoType(); } - MemoryAccessProfile &MemAccessProfile = ErrorOrMemAccesssProfile.get(); + MemoryAccessProfile &MemAccessProfile = ErrorOrMemAccessProfile.get(); uint64_t ArrayStart; if (DispExpr) { @@ -670,15 +670,15 @@ IndirectCallPromotion::MethodInfoType IndirectCallPromotion::maybeGetVtableSyms( }); // Try to get value profiling data for the method load instruction. - auto ErrorOrMemAccesssProfile = + auto ErrorOrMemAccessProfile = BC.MIB->tryGetAnnotationAs(*MethodFetchInsns.back(), "MemoryAccessProfile"); - if (!ErrorOrMemAccesssProfile) { + if (!ErrorOrMemAccessProfile) { DEBUG_VERBOSE(1, dbgs() << "BOLT-INFO: ICP no memory profiling data found\n"); return MethodInfoType(); } - MemoryAccessProfile &MemAccessProfile = ErrorOrMemAccesssProfile.get(); + MemoryAccessProfile &MemAccessProfile = ErrorOrMemAccessProfile.get(); // Find the vtable that each method belongs to. std::map MethodToVtable; diff --git a/bolt/lib/Passes/ReorderData.cpp b/bolt/lib/Passes/ReorderData.cpp index 038cd77..84bf460 100644 --- a/bolt/lib/Passes/ReorderData.cpp +++ b/bolt/lib/Passes/ReorderData.cpp @@ -182,14 +182,14 @@ void ReorderData::assignMemData(BinaryContext &BC) { for (const BinaryBasicBlock &BB : BF) { for (const MCInst &Inst : BB) { - auto ErrorOrMemAccesssProfile = + auto ErrorOrMemAccessProfile = BC.MIB->tryGetAnnotationAs( Inst, "MemoryAccessProfile"); - if (!ErrorOrMemAccesssProfile) + if (!ErrorOrMemAccessProfile) continue; const MemoryAccessProfile &MemAccessProfile = - ErrorOrMemAccesssProfile.get(); + ErrorOrMemAccessProfile.get(); for (const AddressAccess &AccessInfo : MemAccessProfile.AddressAccessInfo) { if (BinaryData *BD = AccessInfo.MemoryObject) { @@ -238,14 +238,14 @@ ReorderData::sortedByFunc(BinaryContext &BC, const BinarySection &Section, continue; for (const MCInst &Inst : BB) { - auto ErrorOrMemAccesssProfile = + auto ErrorOrMemAccessProfile = BC.MIB->tryGetAnnotationAs( Inst, "MemoryAccessProfile"); - if (!ErrorOrMemAccesssProfile) + if (!ErrorOrMemAccessProfile) continue; const MemoryAccessProfile &MemAccessProfile = - ErrorOrMemAccesssProfile.get(); + ErrorOrMemAccessProfile.get(); for (const AddressAccess &AccessInfo : MemAccessProfile.AddressAccessInfo) { if (AccessInfo.MemoryObject) diff --git a/bolt/lib/Passes/RetpolineInsertion.cpp b/bolt/lib/Passes/RetpolineInsertion.cpp index 185cb6b..6bb22e2 100644 --- a/bolt/lib/Passes/RetpolineInsertion.cpp +++ b/bolt/lib/Passes/RetpolineInsertion.cpp @@ -44,19 +44,17 @@ RetpolineLfence("retpoline-lfence", cl::Hidden, cl::cat(BoltCategory)); -cl::opt -R11Availability("r11-availability", - cl::desc("determine the availablity of r11 before indirect branches"), - cl::init(RetpolineInsertion::AvailabilityOptions::NEVER), - cl::values( - clEnumValN(RetpolineInsertion::AvailabilityOptions::NEVER, - "never", "r11 not available"), - clEnumValN(RetpolineInsertion::AvailabilityOptions::ALWAYS, - "always", "r11 avaialable before calls and jumps"), - clEnumValN(RetpolineInsertion::AvailabilityOptions::ABI, - "abi", "r11 avaialable before calls but not before jumps")), - cl::ZeroOrMore, - cl::cat(BoltCategory)); +cl::opt R11Availability( + "r11-availability", + cl::desc("determine the availability of r11 before indirect branches"), + cl::init(RetpolineInsertion::AvailabilityOptions::NEVER), + cl::values(clEnumValN(RetpolineInsertion::AvailabilityOptions::NEVER, + "never", "r11 not available"), + clEnumValN(RetpolineInsertion::AvailabilityOptions::ALWAYS, + "always", "r11 avaialable before calls and jumps"), + clEnumValN(RetpolineInsertion::AvailabilityOptions::ABI, "abi", + "r11 avaialable before calls but not before jumps")), + cl::ZeroOrMore, cl::cat(BoltCategory)); } // namespace opts diff --git a/bolt/lib/RuntimeLibs/HugifyRuntimeLibrary.cpp b/bolt/lib/RuntimeLibs/HugifyRuntimeLibrary.cpp index 9572c96..9a4a1f7 100644 --- a/bolt/lib/RuntimeLibs/HugifyRuntimeLibrary.cpp +++ b/bolt/lib/RuntimeLibs/HugifyRuntimeLibrary.cpp @@ -46,7 +46,7 @@ void HugifyRuntimeLibrary::adjustCommandLineOptions( errs() << "BOLT-ERROR: -hot-text should be applied to binaries with " "pre-compiled manual hugify support, while -hugify will add hugify " - "support automatcally. These two options cannot both be present.\n"; + "support automatically. These two options cannot both be present.\n"; exit(1); } // After the check, we set HotText to be true because automated hugify support