From: Matthias Braun <matze@braunis.de>
Date: Wed, 12 Apr 2017 18:09:05 +0000 (+0000)
Subject: MachineScheduler: Skip acyclic latency heuristic for in-order cores
X-Git-Tag: llvmorg-5.0.0-rc1~7919
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=99551053bd8321d6be10bed3a92e50318214cf81;p=platform%2Fupstream%2Fllvm.git

MachineScheduler: Skip acyclic latency heuristic for in-order cores

The current heuristic is triggered on `InFlightCount > BufferLimit`
which isn't really helpful on in-order cores where BufferLimit is zero.

Note that we already get latency hiding effects for in order cores
by instructions staying in the pending queue on stalls; The additional
latency scheduling heuristics only have minimal effects after that while
occasionally increasing register pressure too much resulting in extra
spills.

My motivation here is additional spills/reloads ending up in a loop in
464.h264ref / BlockMotionSearch function resulting in a 4% overal
regression on an in order core. rdar://30264380

llvm-svn: 300083
---

diff --git a/llvm/lib/CodeGen/MachineScheduler.cpp b/llvm/lib/CodeGen/MachineScheduler.cpp
index fe7b2c8..41e161f71 100644
--- a/llvm/lib/CodeGen/MachineScheduler.cpp
+++ b/llvm/lib/CodeGen/MachineScheduler.cpp
@@ -2729,7 +2729,7 @@ void GenericScheduler::registerRoots() {
     errs() << "Critical Path(GS-RR ): " << Rem.CriticalPath << " \n";
   }
 
-  if (EnableCyclicPath) {
+  if (EnableCyclicPath && SchedModel->getMicroOpBufferSize() > 0) {
     Rem.CyclicCritPath = DAG->computeCyclicCriticalPath();
     checkAcyclicLatency();
   }