From: Tariq Toukan Date: Sun, 16 Dec 2018 15:20:31 +0000 (+0200) Subject: net/mlx5: A write memory barrier is sufficient in EQ ci update X-Git-Tag: v5.4-rc1~1056^2~216^2~2 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=98df6d5b877c26012bbafcf07ff51326db4ef3f7;p=platform%2Fkernel%2Flinux-rpi.git net/mlx5: A write memory barrier is sufficient in EQ ci update Soften the memory barrier call of mb() by a sufficient wmb() in the consumer index update of the event queues. Signed-off-by: Tariq Toukan Signed-off-by: Saeed Mahameed --- diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eq.c b/drivers/net/ethernet/mellanox/mlx5/core/eq.c index 46a747f..e9837ae 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/eq.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/eq.c @@ -707,7 +707,7 @@ void mlx5_eq_update_ci(struct mlx5_eq *eq, u32 cc, bool arm) __raw_writel((__force u32)cpu_to_be32(val), addr); /* We still want ordering, just not swabbing, so add a barrier */ - mb(); + wmb(); } EXPORT_SYMBOL(mlx5_eq_update_ci);