From: Zhigang Gong Date: Mon, 12 Aug 2013 07:53:43 +0000 (+0800) Subject: GBE: set temporary address register for read64 to U64. X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=98bfaa78f5968168d3b12a2a181e6d2aa026f500;p=contrib%2Fbeignet.git GBE: set temporary address register for read64 to U64. Actually, we really use it as two DWORD rather than U64. But if we don't set it to U64, in post scheduler, it doesn't know this is a QWORD register and may cause incorrect scheduling. We can easily trigger this bug when run compiler_vector_double16_load_store with SIMD8 mode. This patch can fix the bug. Signed-off-by: Zhigang Gong --- diff --git a/backend/src/backend/gen_insn_selection.cpp b/backend/src/backend/gen_insn_selection.cpp index 38f56b5..b0dada0 100644 --- a/backend/src/backend/gen_insn_selection.cpp +++ b/backend/src/backend/gen_insn_selection.cpp @@ -2088,7 +2088,7 @@ namespace gbe dst[dstID] = sel.selReg(sel.reg(FAMILY_DWORD)); for ( uint32_t valueID = 0; valueID < valueNum; ++dstID, ++valueID) dst[dstID] = sel.selReg(insn.getValue(valueID)); - sel.READ64(addr, sel.selReg(sel.reg(FAMILY_QWORD)), dst, valueNum + tmpRegNum, valueNum, bti); + sel.READ64(addr, sel.selReg(sel.reg(FAMILY_QWORD), ir::TYPE_U64), dst, valueNum + tmpRegNum, valueNum, bti); } void emitByteGather(Selection::Opaque &sel,