From: Kenneth Graunke <kenneth@whitecape.org>
Date: Sat, 8 Apr 2023 02:19:31 +0000 (-0700)
Subject: intel/compiler: Use nir_dest_bit_size() for ballot bit size check
X-Git-Tag: upstream/23.3.3~10255
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=98bcf650f15f7d6b05b4fd7c6ecf20468e6aaea8;p=platform%2Fupstream%2Fmesa.git

intel/compiler: Use nir_dest_bit_size() for ballot bit size check

There's no guarantee that this is a SSA value.  Use the helper to handle
both SSA values and register correctly.  Otherwise we read trash when we
encounter a register and make bad decisions on types, possibly leading
to our destination being UQ typed when the VGRF is only 32-bit.

Fixes compilation with -Dintel-clc=enabled since 7f6491b76d51f35e7671
(nir: Combine if_uses with instruction uses) but the bug is much older
than that, circa 2017.  We were just getting lucky before.

Fixes: 069bf7c9078a ("i965/fs: Match destination type to size for ballot")
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22374>
---

diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp
index 9f5a849..122a42d 100644
--- a/src/intel/compiler/brw_fs_nir.cpp
+++ b/src/intel/compiler/brw_fs_nir.cpp
@@ -5381,7 +5381,7 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr
       bld.exec_all().group(1, 0).MOV(flag, brw_imm_ud(0u));
       bld.CMP(bld.null_reg_ud(), value, brw_imm_ud(0u), BRW_CONDITIONAL_NZ);
 
-      if (instr->dest.ssa.bit_size > 32) {
+      if (nir_dest_bit_size(instr->dest) > 32) {
          dest.type = BRW_REGISTER_TYPE_UQ;
       } else {
          dest.type = BRW_REGISTER_TYPE_UD;