From: Andrea Di Biagio <andrea.dibiagio@sony.com>
Date: Mon, 31 May 2021 15:39:35 +0000 (+0100)
Subject: [MCA][NFCI] Minor changes to InstrBuilder and Instruction.
X-Git-Tag: llvmorg-14-init~5222
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=9853d0db1e01691562003914f1e803ab0d3a15b2;p=platform%2Fupstream%2Fllvm.git

[MCA][NFCI] Minor changes to InstrBuilder and Instruction.

This is based on the assumption that most simulated instructions don't define
more than one or two registers. This is true for example on x86, where
most instruction definitions don't declare more than one register write.

The default code region size has been increased from 8 to 16. This is based on
the assumption that, for small microbenchmarks, the typical code snippet size is
often less than 16 instructions.

mca::Instruction now uses bitfields to pack flags.
No functional change intended.
---

diff --git a/llvm/include/llvm/MCA/InstrBuilder.h b/llvm/include/llvm/MCA/InstrBuilder.h
index 6900163..04b5cf5 100644
--- a/llvm/include/llvm/MCA/InstrBuilder.h
+++ b/llvm/include/llvm/MCA/InstrBuilder.h
@@ -63,7 +63,8 @@ public:
                const MCRegisterInfo &RI, const MCInstrAnalysis *IA);
 
   void clear() {
-    VariantDescriptors.shrink_and_clear();
+    Descriptors.clear();
+    VariantDescriptors.clear();
     FirstCallInst = true;
     FirstReturnInst = true;
   }
diff --git a/llvm/include/llvm/MCA/Instruction.h b/llvm/include/llvm/MCA/Instruction.h
index cc886a1..f34f31d 100644
--- a/llvm/include/llvm/MCA/Instruction.h
+++ b/llvm/include/llvm/MCA/Instruction.h
@@ -346,7 +346,7 @@ struct ResourceUsage {
 
 /// An instruction descriptor
 struct InstrDesc {
-  SmallVector<WriteDescriptor, 4> Writes; // Implicit writes are at the end.
+  SmallVector<WriteDescriptor, 2> Writes; // Implicit writes are at the end.
   SmallVector<ReadDescriptor, 4> Reads;   // Implicit reads are at the end.
 
   // For every resource used by an instruction of this kind, this vector
@@ -370,16 +370,16 @@ struct InstrDesc {
   // subtarget when computing the reciprocal throughput.
   unsigned SchedClassID;
 
-  bool MayLoad;
-  bool MayStore;
-  bool HasSideEffects;
-  bool BeginGroup;
-  bool EndGroup;
-  bool RetireOOO;
+  unsigned MayLoad : 1;
+  unsigned MayStore : 1;
+  unsigned HasSideEffects : 1;
+  unsigned BeginGroup : 1;
+  unsigned EndGroup : 1;
+  unsigned RetireOOO : 1;
 
   // True if all buffered resources are in-order, and there is at least one
   // buffer which is a dispatch hazard (BufferSize = 0).
-  bool MustIssueImmediately;
+  unsigned MustIssueImmediately : 1;
 
   // A zero latency instruction doesn't consume any scheduler resources.
   bool isZeroLatency() const { return !MaxLatency && Resources.empty(); }
@@ -403,7 +403,7 @@ class InstructionBase {
 
   // Output dependencies.
   // One entry per each implicit and explicit register definition.
-  SmallVector<WriteState, 4> Defs;
+  SmallVector<WriteState, 2> Defs;
 
   // Input dependencies.
   // One entry per each implicit and explicit register use.
diff --git a/llvm/lib/MCA/CodeEmitter.cpp b/llvm/lib/MCA/CodeEmitter.cpp
index dcb92d2..0ce17bd 100644
--- a/llvm/lib/MCA/CodeEmitter.cpp
+++ b/llvm/lib/MCA/CodeEmitter.cpp
@@ -15,8 +15,7 @@
 namespace llvm {
 namespace mca {
 
-CodeEmitter::EncodingInfo
-CodeEmitter::getOrCreateEncodingInfo(unsigned MCID) {
+CodeEmitter::EncodingInfo CodeEmitter::getOrCreateEncodingInfo(unsigned MCID) {
   EncodingInfo &EI = Encodings[MCID];
   if (EI.second)
     return EI;
diff --git a/llvm/lib/MCA/Context.cpp b/llvm/lib/MCA/Context.cpp
index 4ef4907..1433448 100644
--- a/llvm/lib/MCA/Context.cpp
+++ b/llvm/lib/MCA/Context.cpp
@@ -39,13 +39,13 @@ Context::createDefaultPipeline(const PipelineOptions &Opts, SourceMgr &SrcMgr) {
   auto RCU = std::make_unique<RetireControlUnit>(SM);
   auto PRF = std::make_unique<RegisterFile>(SM, MRI, Opts.RegisterFileSize);
   auto LSU = std::make_unique<LSUnit>(SM, Opts.LoadQueueSize,
-                                       Opts.StoreQueueSize, Opts.AssumeNoAlias);
+                                      Opts.StoreQueueSize, Opts.AssumeNoAlias);
   auto HWS = std::make_unique<Scheduler>(SM, *LSU);
 
   // Create the pipeline stages.
   auto Fetch = std::make_unique<EntryStage>(SrcMgr);
-  auto Dispatch = std::make_unique<DispatchStage>(STI, MRI, Opts.DispatchWidth,
-                                                   *RCU, *PRF);
+  auto Dispatch =
+      std::make_unique<DispatchStage>(STI, MRI, Opts.DispatchWidth, *RCU, *PRF);
   auto Execute =
       std::make_unique<ExecuteStage>(*HWS, Opts.EnableBottleneckAnalysis);
   auto Retire = std::make_unique<RetireStage>(*RCU, *PRF, *LSU);
diff --git a/llvm/tools/llvm-mca/CodeRegion.h b/llvm/tools/llvm-mca/CodeRegion.h
index d2b05fa..0b25907 100644
--- a/llvm/tools/llvm-mca/CodeRegion.h
+++ b/llvm/tools/llvm-mca/CodeRegion.h
@@ -53,7 +53,7 @@ class CodeRegion {
   // An optional descriptor for this region.
   llvm::StringRef Description;
   // Instructions that form this region.
-  llvm::SmallVector<llvm::MCInst, 8> Instructions;
+  llvm::SmallVector<llvm::MCInst, 16> Instructions;
   // Source location range.
   llvm::SMLoc RangeStart;
   llvm::SMLoc RangeEnd;