From: Florian Hahn Date: Sun, 20 Mar 2022 10:11:40 +0000 (+0000) Subject: [VPlan] Add test for VPExpandSCEVRecipe printing. X-Git-Tag: upstream/15.0.7~12992 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=973183612ea26bdc2394863f38a46514c33dc026;p=platform%2Fupstream%2Fllvm.git [VPlan] Add test for VPExpandSCEVRecipe printing. --- diff --git a/llvm/test/Transforms/LoopVectorize/vplan-printing.ll b/llvm/test/Transforms/LoopVectorize/vplan-printing.ll index afe7e6f..bc6ba17 100644 --- a/llvm/test/Transforms/LoopVectorize/vplan-printing.ll +++ b/llvm/test/Transforms/LoopVectorize/vplan-printing.ll @@ -391,6 +391,49 @@ exit: declare float @llvm.sqrt.f32(float) nounwind readnone declare float @llvm.fmuladd.f32(float, float, float) +define void @print_expand_scev(i64 %y, i8* %ptr) { +; CHECK-LABEL: Checking a loop in 'print_expand_scev' +; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' { +; CHECK-NEXT: Live-in vp<%0> = vector-trip-count +; CHECK-EMPTY: +; CHECK-NEXT: vector loop: { +; CHECK-NEXT: loop: +; CHECK-NEXT: EMIT vp<[[CAN_IV:%.+]]> = CANONICAL-INDUCTION +; CHECK-NEXT: WIDEN-INDUCTION\l" + +; CHECK-NEXT: " %iv = phi %iv.next, 0\l" + +; CHECK-NEXT: " ir<%v2> +; CHECK-NEXT: EMIT vp<[[EXP_SCEV:%.+]]> = EXPAND SCEV (1 + (%y /u 492802768830814060)) +; CHECK-NEXT: vp<[[STEPS:%.+]]> = SCALAR-STEPS vp<[[CAN_IV]]>, ir<0>, vp<[[EXP_SCEV]]> +; CHECK-NEXT: WIDEN ir<%v3> = add ir<%v2>, ir<1> +; CHECK-NEXT: REPLICATE ir<%gep> = getelementptr ir<%ptr>, vp<[[STEPS]]> +; CHECK-NEXT: REPLICATE store ir<%v3>, ir<%gep> +; CHECK-NEXT: EMIT vp<[[CAN_INC:%.+]]> = VF * UF +(nuw) vp<[[CAN_IV]]> +; CHECK-NEXT: EMIT branch-on-count vp<[[CAN_INC]]> vp<%0> +; CHECK-NEXT: No successors +; CHECK-NEXT: } +; CHECK-NEXT: No successors +; CHECK-NEXT: } +; +entry: + %div = udiv i64 %y, 492802768830814060 + %inc = add i64 %div, 1 + br label %loop + +loop: ; preds = %loop, %entry + %iv = phi i64 [ %iv.next, %loop ], [ 0, %entry ] + %v2 = trunc i64 %iv to i8 + %v3 = add i8 %v2, 1 + %gep = getelementptr inbounds i8, i8* %ptr, i64 %iv + store i8 %v3, i8* %gep + + %cmp15 = icmp slt i8 %v3, 10000 + %iv.next = add i64 %iv, %inc + br i1 %cmp15, label %loop, label %loop.exit + +loop.exit: + ret void +} + !llvm.dbg.cu = !{!0} !llvm.module.flags = !{!3, !4}