From: Tirumalesh Chalamarla Date: Tue, 22 Sep 2015 17:59:48 +0000 (+0200) Subject: arm64: Increase the max granular size X-Git-Tag: v4.14-rc1~4321^2~19 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=97303480753e48fb313dc0e15daaf11b0451cdb8;p=platform%2Fkernel%2Flinux-rpi.git arm64: Increase the max granular size Increase the standard cacheline size to avoid having locks in the same cacheline. Cavium's ThunderX core implements cache lines of 128 byte size. With current granulare size of 64 bytes (L1_CACHE_SHIFT=6) two locks could share the same cache line leading a performance degradation. Increasing the size fixes that. Increasing the size has no negative impact to cache invalidation on systems with a smaller cache line. There is an impact on memory usage, but that's not too important for arm64 use cases. Signed-off-by: Tirumalesh Chalamarla Signed-off-by: Robert Richter Acked-by: Timur Tabi Signed-off-by: Catalin Marinas --- diff --git a/arch/arm64/include/asm/cache.h b/arch/arm64/include/asm/cache.h index bde4499..5082b30 100644 --- a/arch/arm64/include/asm/cache.h +++ b/arch/arm64/include/asm/cache.h @@ -18,7 +18,7 @@ #include -#define L1_CACHE_SHIFT 6 +#define L1_CACHE_SHIFT 7 #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) /*