From: Tilmann Scheller <t.scheller@samsung.com>
Date: Thu, 24 Jul 2014 09:55:46 +0000 (+0000)
Subject: [ARM] Make the assembler reject unpredictable pre/post-indexed ARM STRH instructions.
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=96ef72e54abff11b81fa53a57e22ab4c5bef27d8;p=platform%2Fupstream%2Fllvm.git

[ARM] Make the assembler reject unpredictable pre/post-indexed ARM STRH instructions.

The ARM ARM prohibits STRH instructions with writeback into the source register. With this commit this constraint is now enforced and we stop assembling STRH instructions with unpredictable behavior.

llvm-svn: 213850
---

diff --git a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
index ccef6c3..e34282b 100644
--- a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -5732,6 +5732,8 @@ bool ARMAsmParser::validateInstruction(MCInst &Inst,
   case ARM::STR_PRE_REG:
   case ARM::STR_POST_IMM:
   case ARM::STR_POST_REG:
+  case ARM::STRH_PRE:
+  case ARM::STRH_POST:
   case ARM::STRB_PRE_IMM:
   case ARM::STRB_PRE_REG:
   case ARM::STRB_POST_IMM:
diff --git a/llvm/test/MC/ARM/diagnostics.s b/llvm/test/MC/ARM/diagnostics.s
index 25eb6f2..83af10d 100644
--- a/llvm/test/MC/ARM/diagnostics.s
+++ b/llvm/test/MC/ARM/diagnostics.s
@@ -496,6 +496,10 @@ foo2:
         str r0, [r0, r1]!
         str r0, [r0], #4
         str r0, [r0], r1
+        strh r0, [r0, #2]!
+        strh r0, [r0, r1]!
+        strh r0, [r0], #2
+        strh r0, [r0], r1
         strb r0, [r0, #1]!
         strb r0, [r0, r1]!
         strb r0, [r0], #1
@@ -513,6 +517,18 @@ foo2:
 @ CHECK-ERRORS: str r0, [r0], r1
 @ CHECK-ERRORS:         ^
 @ CHECK-ERRORS: error: source register and base register can't be identical
+@ CHECK-ERRORS: strh r0, [r0, #2]!
+@ CHECK-ERRORS:          ^
+@ CHECK-ERRORS: error: source register and base register can't be identical
+@ CHECK-ERRORS: strh r0, [r0, r1]!
+@ CHECK-ERRORS:          ^
+@ CHECK-ERRORS: error: source register and base register can't be identical
+@ CHECK-ERRORS: strh r0, [r0], #2
+@ CHECK-ERRORS:          ^
+@ CHECK-ERRORS: error: source register and base register can't be identical
+@ CHECK-ERRORS: strh r0, [r0], r1
+@ CHECK-ERRORS:          ^
+@ CHECK-ERRORS: error: source register and base register can't be identical
 @ CHECK-ERRORS: strb r0, [r0, #1]!
 @ CHECK-ERRORS:          ^
 @ CHECK-ERRORS: error: source register and base register can't be identical