From: Michal Simek <michal.simek@xilinx.com>
Date: Mon, 20 Jan 2014 10:05:37 +0000 (+0100)
Subject: zynq: Update CLK in bdinfo
X-Git-Tag: submit/tizen_2.3.1/20150915.092117~1^2~18^2~2
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=96a5d4dc1ec1ce26b32a3fa294816a47b62ae68a;p=kernel%2Fu-boot.git

zynq: Update CLK in bdinfo

ARM has specific clk entries which should be also setup.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---

diff --git a/arch/arm/cpu/armv7/zynq/clk.c b/arch/arm/cpu/armv7/zynq/clk.c
index 4307111..d2885dc 100644
--- a/arch/arm/cpu/armv7/zynq/clk.c
+++ b/arch/arm/cpu/armv7/zynq/clk.c
@@ -161,6 +161,8 @@ static void init_ddr_clocks(void)
 	clks[dci_clk].frequency = DIV_ROUND_CLOSEST(
 			DIV_ROUND_CLOSEST(prate, div0), div1);
 	clks[dci_clk].name = "dci";
+
+	gd->bd->bi_ddr_freq = clks[ddr3x_clk].frequency / 1000000;
 }
 
 static void init_cpu_clocks(void)
@@ -593,6 +595,9 @@ int set_cpu_clk_info(void)
 	init_periph_clocks();
 	init_aper_clocks();
 
+	gd->bd->bi_arm_freq = gd->cpu_clk / 1000000;
+	gd->bd->bi_dsp_freq = 0;
+
 	return 0;
 }