From: Kevin Cernekee <cernekee@gmail.com>
Date: Sat, 19 Sep 2009 02:12:45 +0000 (-0700)
Subject: MIPS: MIPSxx SC: Avoid destructive invalidation on partial L2 cachelines.
X-Git-Tag: v2.6.32-rc3~58^2~10
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=96983ffefce46312e9372d357309dda413553009;p=platform%2Fkernel%2Flinux-stable.git

MIPS: MIPSxx SC: Avoid destructive invalidation on partial L2 cachelines.

This extends commit a8ca8b64e3fdfec17679cba0ca5ce6e3ffed092d to cover
MIPSxx-style board cache code.

Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
---

diff --git a/arch/mips/mm/sc-mips.c b/arch/mips/mm/sc-mips.c
index b55c2d1..5ab5fa8 100644
--- a/arch/mips/mm/sc-mips.c
+++ b/arch/mips/mm/sc-mips.c
@@ -32,6 +32,11 @@ static void mips_sc_wback_inv(unsigned long addr, unsigned long size)
  */
 static void mips_sc_inv(unsigned long addr, unsigned long size)
 {
+	unsigned long lsize = cpu_scache_line_size();
+	unsigned long almask = ~(lsize - 1);
+
+	cache_op(Hit_Writeback_Inv_SD, addr & almask);
+	cache_op(Hit_Writeback_Inv_SD, (addr + size - 1) & almask);
 	blast_inv_scache_range(addr, addr + size);
 }