From: Jonas Paulsson Date: Sat, 10 Jul 2021 09:15:12 +0000 (+0200) Subject: [SystemZ] Bugfix for the 'N' code for inline asm operand. X-Git-Tag: llvmorg-14-init~1760 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=96421af5f8b48a35f5375a026c9fbc14cb18a178;p=platform%2Fupstream%2Fllvm.git [SystemZ] Bugfix for the 'N' code for inline asm operand. Don't use a local MachineOperand copy in SystemZAsmPrinter::PrintAsmOperand() and change the register as it may break the MRI tracking of register uses. Use an MCOperand instead. Review: Ulrich Weigand Differential Revision: https://reviews.llvm.org/D105757 --- diff --git a/llvm/lib/Target/SystemZ/SystemZAsmPrinter.cpp b/llvm/lib/Target/SystemZ/SystemZAsmPrinter.cpp index f17d53e..46ccd21 100644 --- a/llvm/lib/Target/SystemZ/SystemZAsmPrinter.cpp +++ b/llvm/lib/Target/SystemZ/SystemZAsmPrinter.cpp @@ -765,16 +765,19 @@ bool SystemZAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, const char *ExtraCode, raw_ostream &OS) { const MCRegisterInfo &MRI = *TM.getMCRegisterInfo(); - MachineOperand MO = MI->getOperand(OpNo); + const MachineOperand &MO = MI->getOperand(OpNo); + MCOperand MCOp; if (ExtraCode) { if (ExtraCode[0] == 'N' && !ExtraCode[1] && MO.isReg() && SystemZ::GR128BitRegClass.contains(MO.getReg())) - MO.setReg(MRI.getSubReg(MO.getReg(), SystemZ::subreg_l64)); + MCOp = + MCOperand::createReg(MRI.getSubReg(MO.getReg(), SystemZ::subreg_l64)); else return AsmPrinter::PrintAsmOperand(MI, OpNo, ExtraCode, OS); + } else { + SystemZMCInstLower Lower(MF->getContext(), *this); + MCOp = Lower.lowerOperand(MO); } - SystemZMCInstLower Lower(MF->getContext(), *this); - MCOperand MCOp(Lower.lowerOperand(MO)); SystemZInstPrinter::printOperand(MCOp, MAI, OS); return false; } diff --git a/llvm/test/CodeGen/SystemZ/inline-asm-i128.ll b/llvm/test/CodeGen/SystemZ/inline-asm-i128.ll index 84e3f7d..1a6b764 100644 --- a/llvm/test/CodeGen/SystemZ/inline-asm-i128.ll +++ b/llvm/test/CodeGen/SystemZ/inline-asm-i128.ll @@ -135,3 +135,24 @@ entry: %Res = tail call i64 asm "\09lgr\09$0,${1:N}", "=d,d"(i128 %Ins) ret i64 %Res } + +; Test 'N' with multiple accesses to the same operand and i128 result. +@V128 = global i128 0, align 16 +define i32 @fun6() { +; CHECK-LABEL: fun6: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: lgrl %r1, V128@GOT +; CHECK-NEXT: lg %r3, 8(%r1) +; CHECK-NEXT: lg %r2, 0(%r1) +; CHECK-NEXT: #APP +; CHECK-NEXT: ltgr %r3,%r3 +; CHECK-NEXT: #NO_APP +; CHECK-NEXT: stg %r2, 0(%r1) +; CHECK-NEXT: stg %r3, 8(%r1) +; CHECK-NEXT: br %r14 +entry: + %0 = load i128, i128* @V128 + %1 = tail call i128 asm "ltgr ${0:N},${0:N}", "=&d,0"(i128 %0) + store i128 %1, i128* @V128 + ret i32 undef +}