From: Ben Shi <powerman1st@163.com>
Date: Mon, 23 Aug 2021 13:09:12 +0000 (+0800)
Subject: [RISCV][test] Add more tests for (mul (add x, c1), c2)
X-Git-Tag: upstream/15.0.7~32441
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=9621bbdf62d35b30fbe5a7a26028970bbed5de68;p=platform%2Fupstream%2Fllvm.git

[RISCV][test] Add more tests for (mul (add x, c1), c2)

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D108606
---

diff --git a/llvm/test/CodeGen/RISCV/addimm-mulimm.ll b/llvm/test/CodeGen/RISCV/addimm-mulimm.ll
index e56b037..28e2a0b 100644
--- a/llvm/test/CodeGen/RISCV/addimm-mulimm.ll
+++ b/llvm/test/CodeGen/RISCV/addimm-mulimm.ll
@@ -338,3 +338,225 @@ define i64 @add_mul_combine_reject_d3(i64 %x) {
   %tmp1 = mul i64 %tmp0, 192
   ret i64 %tmp1
 }
+
+define i32 @add_mul_combine_reject_e1(i32 %x) {
+; RV32IMB-LABEL: add_mul_combine_reject_e1:
+; RV32IMB:       # %bb.0:
+; RV32IMB-NEXT:    addi a1, zero, 29
+; RV32IMB-NEXT:    mul a0, a0, a1
+; RV32IMB-NEXT:    lui a1, 14
+; RV32IMB-NEXT:    addi a1, a1, -185
+; RV32IMB-NEXT:    add a0, a0, a1
+; RV32IMB-NEXT:    ret
+;
+; RV64IMB-LABEL: add_mul_combine_reject_e1:
+; RV64IMB:       # %bb.0:
+; RV64IMB-NEXT:    addi a1, zero, 29
+; RV64IMB-NEXT:    mulw a0, a0, a1
+; RV64IMB-NEXT:    lui a1, 14
+; RV64IMB-NEXT:    addiw a1, a1, -185
+; RV64IMB-NEXT:    addw a0, a0, a1
+; RV64IMB-NEXT:    ret
+  %tmp0 = mul i32 %x, 29
+  %tmp1 = add i32 %tmp0, 57159
+  ret i32 %tmp1
+}
+
+define signext i32 @add_mul_combine_reject_e2(i32 signext %x) {
+; RV32IMB-LABEL: add_mul_combine_reject_e2:
+; RV32IMB:       # %bb.0:
+; RV32IMB-NEXT:    addi a1, zero, 29
+; RV32IMB-NEXT:    mul a0, a0, a1
+; RV32IMB-NEXT:    lui a1, 14
+; RV32IMB-NEXT:    addi a1, a1, -185
+; RV32IMB-NEXT:    add a0, a0, a1
+; RV32IMB-NEXT:    ret
+;
+; RV64IMB-LABEL: add_mul_combine_reject_e2:
+; RV64IMB:       # %bb.0:
+; RV64IMB-NEXT:    addi a1, zero, 29
+; RV64IMB-NEXT:    mulw a0, a0, a1
+; RV64IMB-NEXT:    lui a1, 14
+; RV64IMB-NEXT:    addiw a1, a1, -185
+; RV64IMB-NEXT:    addw a0, a0, a1
+; RV64IMB-NEXT:    ret
+  %tmp0 = mul i32 %x, 29
+  %tmp1 = add i32 %tmp0, 57159
+  ret i32 %tmp1
+}
+
+define i64 @add_mul_combine_reject_e3(i64 %x) {
+; RV32IMB-LABEL: add_mul_combine_reject_e3:
+; RV32IMB:       # %bb.0:
+; RV32IMB-NEXT:    addi a2, zero, 29
+; RV32IMB-NEXT:    mul a1, a1, a2
+; RV32IMB-NEXT:    mulhu a3, a0, a2
+; RV32IMB-NEXT:    add a1, a3, a1
+; RV32IMB-NEXT:    mul a2, a0, a2
+; RV32IMB-NEXT:    lui a0, 14
+; RV32IMB-NEXT:    addi a0, a0, -185
+; RV32IMB-NEXT:    add a0, a2, a0
+; RV32IMB-NEXT:    sltu a2, a0, a2
+; RV32IMB-NEXT:    add a1, a1, a2
+; RV32IMB-NEXT:    ret
+;
+; RV64IMB-LABEL: add_mul_combine_reject_e3:
+; RV64IMB:       # %bb.0:
+; RV64IMB-NEXT:    addi a1, zero, 29
+; RV64IMB-NEXT:    mul a0, a0, a1
+; RV64IMB-NEXT:    lui a1, 14
+; RV64IMB-NEXT:    addiw a1, a1, -185
+; RV64IMB-NEXT:    add a0, a0, a1
+; RV64IMB-NEXT:    ret
+  %tmp0 = mul i64 %x, 29
+  %tmp1 = add i64 %tmp0, 57159
+  ret i64 %tmp1
+}
+
+define i32 @add_mul_combine_reject_f1(i32 %x) {
+; RV32IMB-LABEL: add_mul_combine_reject_f1:
+; RV32IMB:       # %bb.0:
+; RV32IMB-NEXT:    addi a1, zero, 29
+; RV32IMB-NEXT:    mul a0, a0, a1
+; RV32IMB-NEXT:    lui a1, 14
+; RV32IMB-NEXT:    addi a1, a1, -145
+; RV32IMB-NEXT:    add a0, a0, a1
+; RV32IMB-NEXT:    ret
+;
+; RV64IMB-LABEL: add_mul_combine_reject_f1:
+; RV64IMB:       # %bb.0:
+; RV64IMB-NEXT:    addi a1, zero, 29
+; RV64IMB-NEXT:    mulw a0, a0, a1
+; RV64IMB-NEXT:    lui a1, 14
+; RV64IMB-NEXT:    addiw a1, a1, -145
+; RV64IMB-NEXT:    addw a0, a0, a1
+; RV64IMB-NEXT:    ret
+  %tmp0 = mul i32 %x, 29
+  %tmp1 = add i32 %tmp0, 57199
+  ret i32 %tmp1
+}
+
+define signext i32 @add_mul_combine_reject_f2(i32 signext %x) {
+; RV32IMB-LABEL: add_mul_combine_reject_f2:
+; RV32IMB:       # %bb.0:
+; RV32IMB-NEXT:    addi a1, zero, 29
+; RV32IMB-NEXT:    mul a0, a0, a1
+; RV32IMB-NEXT:    lui a1, 14
+; RV32IMB-NEXT:    addi a1, a1, -145
+; RV32IMB-NEXT:    add a0, a0, a1
+; RV32IMB-NEXT:    ret
+;
+; RV64IMB-LABEL: add_mul_combine_reject_f2:
+; RV64IMB:       # %bb.0:
+; RV64IMB-NEXT:    addi a1, zero, 29
+; RV64IMB-NEXT:    mulw a0, a0, a1
+; RV64IMB-NEXT:    lui a1, 14
+; RV64IMB-NEXT:    addiw a1, a1, -145
+; RV64IMB-NEXT:    addw a0, a0, a1
+; RV64IMB-NEXT:    ret
+  %tmp0 = mul i32 %x, 29
+  %tmp1 = add i32 %tmp0, 57199
+  ret i32 %tmp1
+}
+
+define i64 @add_mul_combine_reject_f3(i64 %x) {
+; RV32IMB-LABEL: add_mul_combine_reject_f3:
+; RV32IMB:       # %bb.0:
+; RV32IMB-NEXT:    addi a2, zero, 29
+; RV32IMB-NEXT:    mul a1, a1, a2
+; RV32IMB-NEXT:    mulhu a3, a0, a2
+; RV32IMB-NEXT:    add a1, a3, a1
+; RV32IMB-NEXT:    mul a2, a0, a2
+; RV32IMB-NEXT:    lui a0, 14
+; RV32IMB-NEXT:    addi a0, a0, -145
+; RV32IMB-NEXT:    add a0, a2, a0
+; RV32IMB-NEXT:    sltu a2, a0, a2
+; RV32IMB-NEXT:    add a1, a1, a2
+; RV32IMB-NEXT:    ret
+;
+; RV64IMB-LABEL: add_mul_combine_reject_f3:
+; RV64IMB:       # %bb.0:
+; RV64IMB-NEXT:    addi a1, zero, 29
+; RV64IMB-NEXT:    mul a0, a0, a1
+; RV64IMB-NEXT:    lui a1, 14
+; RV64IMB-NEXT:    addiw a1, a1, -145
+; RV64IMB-NEXT:    add a0, a0, a1
+; RV64IMB-NEXT:    ret
+  %tmp0 = mul i64 %x, 29
+  %tmp1 = add i64 %tmp0, 57199
+  ret i64 %tmp1
+}
+
+define i32 @add_mul_combine_reject_g1(i32 %x) {
+; RV32IMB-LABEL: add_mul_combine_reject_g1:
+; RV32IMB:       # %bb.0:
+; RV32IMB-NEXT:    sh3add a1, a0, a0
+; RV32IMB-NEXT:    sh3add a0, a1, a0
+; RV32IMB-NEXT:    lui a1, 2
+; RV32IMB-NEXT:    addi a1, a1, -882
+; RV32IMB-NEXT:    add a0, a0, a1
+; RV32IMB-NEXT:    ret
+;
+; RV64IMB-LABEL: add_mul_combine_reject_g1:
+; RV64IMB:       # %bb.0:
+; RV64IMB-NEXT:    sh3add a1, a0, a0
+; RV64IMB-NEXT:    sh3add a0, a1, a0
+; RV64IMB-NEXT:    lui a1, 2
+; RV64IMB-NEXT:    addiw a1, a1, -882
+; RV64IMB-NEXT:    addw a0, a0, a1
+; RV64IMB-NEXT:    ret
+  %tmp0 = mul i32 %x, 73
+  %tmp1 = add i32 %tmp0, 7310
+  ret i32 %tmp1
+}
+
+define signext i32 @add_mul_combine_reject_g2(i32 signext %x) {
+; RV32IMB-LABEL: add_mul_combine_reject_g2:
+; RV32IMB:       # %bb.0:
+; RV32IMB-NEXT:    sh3add a1, a0, a0
+; RV32IMB-NEXT:    sh3add a0, a1, a0
+; RV32IMB-NEXT:    lui a1, 2
+; RV32IMB-NEXT:    addi a1, a1, -882
+; RV32IMB-NEXT:    add a0, a0, a1
+; RV32IMB-NEXT:    ret
+;
+; RV64IMB-LABEL: add_mul_combine_reject_g2:
+; RV64IMB:       # %bb.0:
+; RV64IMB-NEXT:    sh3add a1, a0, a0
+; RV64IMB-NEXT:    sh3add a0, a1, a0
+; RV64IMB-NEXT:    lui a1, 2
+; RV64IMB-NEXT:    addiw a1, a1, -882
+; RV64IMB-NEXT:    addw a0, a0, a1
+; RV64IMB-NEXT:    ret
+  %tmp0 = mul i32 %x, 73
+  %tmp1 = add i32 %tmp0, 7310
+  ret i32 %tmp1
+}
+
+define i64 @add_mul_combine_reject_g3(i64 %x) {
+; RV32IMB-LABEL: add_mul_combine_reject_g3:
+; RV32IMB:       # %bb.0:
+; RV32IMB-NEXT:    addi a2, zero, 73
+; RV32IMB-NEXT:    mul a1, a1, a2
+; RV32IMB-NEXT:    mulhu a3, a0, a2
+; RV32IMB-NEXT:    add a1, a3, a1
+; RV32IMB-NEXT:    mul a2, a0, a2
+; RV32IMB-NEXT:    lui a0, 2
+; RV32IMB-NEXT:    addi a0, a0, -882
+; RV32IMB-NEXT:    add a0, a2, a0
+; RV32IMB-NEXT:    sltu a2, a0, a2
+; RV32IMB-NEXT:    add a1, a1, a2
+; RV32IMB-NEXT:    ret
+;
+; RV64IMB-LABEL: add_mul_combine_reject_g3:
+; RV64IMB:       # %bb.0:
+; RV64IMB-NEXT:    sh3add a1, a0, a0
+; RV64IMB-NEXT:    sh3add a0, a1, a0
+; RV64IMB-NEXT:    lui a1, 2
+; RV64IMB-NEXT:    addiw a1, a1, -882
+; RV64IMB-NEXT:    add a0, a0, a1
+; RV64IMB-NEXT:    ret
+  %tmp0 = mul i64 %x, 73
+  %tmp1 = add i64 %tmp0, 7310
+  ret i64 %tmp1
+}