From: Guillaume Emont <guijemont@igalia.com>
Date: Fri, 30 Nov 2012 18:23:17 +0000 (+0100)
Subject: mips: implement convsbw
X-Git-Tag: orc-0.4.17~52
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=95b725344658199740297a0fe150122e7fae3a47;p=platform%2Fupstream%2Forc.git

mips: implement convsbw
---

diff --git a/orc/orcrules-mips.c b/orc/orcrules-mips.c
index ad0a261..8b63c44 100644
--- a/orc/orcrules-mips.c
+++ b/orc/orcrules-mips.c
@@ -206,6 +206,18 @@ mips_rule_convssslw (OrcCompiler *compiler, void *user, OrcInstruction *insn)
 }
 
 void
+mips_rule_convsbw (OrcCompiler *compiler, void *user, OrcInstruction *insn)
+{
+  int src = ORC_SRC_ARG (compiler, insn, 0);
+  int dest = ORC_DEST_ARG (compiler, insn, 0);
+
+  /* left shift 8 bits, then right shift signed 8 bits, so that the sign bit
+   * gets replicated in the upper 8 bits */
+  orc_mips_emit_shll_ph (compiler, dest, src, 8);
+  orc_mips_emit_shra_ph (compiler, dest, dest, 8);
+}
+
+void
 mips_rule_mergewl (OrcCompiler *compiler, void *user, OrcInstruction *insn)
 {
   int src1 = ORC_SRC_ARG (compiler, insn, 0);
@@ -291,6 +303,7 @@ orc_compiler_orc_mips_register_rules (OrcTarget *target)
   orc_rule_register (rule_set, "mulswl", mips_rule_mul, NULL);
   orc_rule_register (rule_set, "shrsl", mips_rule_shrs, NULL);
   orc_rule_register (rule_set, "convssslw", mips_rule_convssslw, NULL);
+  orc_rule_register (rule_set, "convsbw", mips_rule_convsbw, NULL);
   orc_rule_register (rule_set, "mergewl", mips_rule_mergewl, NULL);
   orc_rule_register (rule_set, "addssw", mips_rule_addssw, NULL);
 }