From: Aleksandr Korolev <aleksandr.korolev@intel.com>
Date: Tue, 17 Nov 2020 08:36:23 +0000 (+0300)
Subject: [IE][VPU]: Fix condition in HW tiling (#3111)
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=957a1f65905e3e25713516d7ecb240006edd41f2;p=platform%2Fupstream%2Fdldt.git

[IE][VPU]: Fix condition in HW tiling (#3111)

Co-authored-by: kora6 <kora6@github.com>
---

diff --git a/inference-engine/src/vpu/graph_transformer/src/middleend/hw/tiling.cpp b/inference-engine/src/vpu/graph_transformer/src/middleend/hw/tiling.cpp
index d2be8f2..2da235b 100644
--- a/inference-engine/src/vpu/graph_transformer/src/middleend/hw/tiling.cpp
+++ b/inference-engine/src/vpu/graph_transformer/src/middleend/hw/tiling.cpp
@@ -430,17 +430,12 @@ bool checkHWRestrictions(
         int kernelSizeX, int kernelSizeY,
         int kernelStride,
         HwOpMode mode, HwOpType type) {
-    // Workaround for HW ops failure if too wide input:
-    // Looks like HW operations (primarily Pooling) can
-    // use only part of available CMX, up to 1014 * 128
-    // bits (i.e. 1014 * 16 bytes)
-    // Provided HwOpMode is 16x16, this means HW needs
-    // to read up to 16 lines of input tensor, so each
-    // line mustn't exceed 1014 bytes or 507 pixels if
-    // precision is FP16
+    // Workaround for HW ops failure if too wide input
+    // widht and  small height
     // More details available with the ticket #-33366
-    if (inTileWidth > 507) {
-        return false;
+
+    if (inTileWidth > 507 && inTileHeight < 64 && type != HwOpType::POOL) {
+                return false;
     }
 
     const int chansPerBlock = 1 << static_cast<int>(mode);