From: Zong Li <zong@andestech.com>
Date: Thu, 2 Aug 2018 15:21:56 +0000 (+0800)
Subject: RISC-V: Add the directive for alignment of stvec's value
X-Git-Tag: v4.19~358^2~4
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=94f592f0e5b9c17a7505119a2d6c0f1f529ae93d;p=platform%2Fkernel%2Flinux-rpi.git

RISC-V: Add the directive for alignment of stvec's value

The stvec's value must be 4 byte alignment by specification definition.
These directives avoid to stvec be set the non-alignment value.

Signed-off-by: Zong Li <zong@andestech.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
---

diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S
index 6e07ed3..c4d2c63 100644
--- a/arch/riscv/kernel/head.S
+++ b/arch/riscv/kernel/head.S
@@ -94,6 +94,7 @@ relocate:
 	or a0, a0, a1
 	sfence.vma
 	csrw sptbr, a0
+.align 2
 1:
 	/* Set trap vector to spin forever to help debug */
 	la a0, .Lsecondary_park
@@ -143,6 +144,7 @@ relocate:
 	tail smp_callin
 #endif
 
+.align 2
 .Lsecondary_park:
 	/* We lack SMP support or have too many harts, so park this hart */
 	wfi