From: Simon Pilgrim <llvm-dev@redking.me.uk>
Date: Sun, 20 Nov 2022 10:48:27 +0000 (+0000)
Subject: [X86] Remove unnecessary zmm shuffle instruction overrides from IceLake model
X-Git-Tag: upstream/17.0.6~27078
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=94d240a44a52dc4dfed52e0719ab4a728cdbdb4d;p=platform%2Fupstream%2Fllvm.git

[X86] Remove unnecessary zmm shuffle instruction overrides from IceLake model

Reported by D138359 and confirmed with Intel AoM, Agner + uops.info
---

diff --git a/llvm/lib/Target/X86/X86SchedIceLake.td b/llvm/lib/Target/X86/X86SchedIceLake.td
index a05b2f5e..8b66b02 100644
--- a/llvm/lib/Target/X86/X86SchedIceLake.td
+++ b/llvm/lib/Target/X86/X86SchedIceLake.td
@@ -668,12 +668,12 @@ def: InstRW<[ICXWriteResGroup3], (instregex "COM(P?)_FST0r",
                                             "VPBROADCAST(D|Q)rr",
                                             "(V?)INSERTPS(Z?)rr",
                                             "(V?)MOV(HL|LH)PS(Z?)rr",
-                                            "(V?)MOVDDUP(Y|Z|Z128|Z256)?rr",
-                                            "(V?)PALIGNR(Y|Z|Z128|Z256)?rri",
-                                            "(V?)PERMIL(PD|PS)(Y|Z|Z128|Z256)?ri",
-                                            "(V?)PERMIL(PD|PS)(Y|Z|Z128|Z256)?rr",
+                                            "(V?)MOVDDUP(Y|Z128|Z256)?rr",
+                                            "(V?)PALIGNR(Y|Z128|Z256)?rri",
+                                            "(V?)PERMIL(PD|PS)(Y|Z128|Z256)?ri",
+                                            "(V?)PERMIL(PD|PS)(Y|Z128|Z256)?rr",
                                             "(V?)PACK(U|S)S(DW|WB)(Y|Z|Z128|Z256)?rr",
-                                            "(V?)UNPCK(L|H)(PD|PS)(Y|Z|Z128|Z256)?rr")>;
+                                            "(V?)UNPCK(L|H)(PD|PS)(Y|Z128|Z256)?rr")>;
 
 def ICXWriteResGroup4 : SchedWriteRes<[ICXPort6]> {
   let Latency = 1;
@@ -1539,11 +1539,11 @@ def ICXWriteResGroup119 : SchedWriteRes<[ICXPort5,ICXPort23]> {
 def: InstRW<[ICXWriteResGroup119], (instregex "FCOM(P?)(32|64)m",
                                               "VPBROADCASTB(Z|Z256)rm(b?)",
                                               "VPBROADCASTW(Z|Z256)rm(b?)",
-                                              "(V?)PALIGNR(Y|Z|Z256)rmi",
-                                              "(V?)PERMIL(PD|PS)(Y|Z|Z256)m(b?)i",
-                                              "(V?)PERMIL(PD|PS)(Y|Z|Z256)rm",
+                                              "(V?)PALIGNR(Y|Z256)rmi",
+                                              "(V?)PERMIL(PD|PS)(Y|Z256)m(b?)i",
+                                              "(V?)PERMIL(PD|PS)(Y|Z256)rm",
                                               "(V?)PACK(U|S)S(DW|WB)(Y|Z|Z256)rm",
-                                              "(V?)UNPCK(L|H)(PD|PS)(Y|Z|Z256)rm")>;
+                                              "(V?)UNPCK(L|H)(PD|PS)(Y|Z256)rm")>;
 def: InstRW<[ICXWriteResGroup119], (instrs VPBROADCASTBYrm,
                                            VPBROADCASTWYrm,
                                            VPMOVSXBDYrm,