From: Lionel Landwerlin Date: Mon, 12 Dec 2022 13:31:41 +0000 (+0200) Subject: intel/fs: make Wa_1806565034 conditional to non robust access X-Git-Tag: upstream/23.3.3~15608 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=94bb4a13fa294204e32b88a098c2d49a0c82a5c3;p=platform%2Fupstream%2Fmesa.git intel/fs: make Wa_1806565034 conditional to non robust access Signed-off-by: Lionel Landwerlin Reviewed-by: Ivan Briano Part-of: --- diff --git a/src/gallium/drivers/crocus/crocus_program.c b/src/gallium/drivers/crocus/crocus_program.c index 753d37e..404c42b 100644 --- a/src/gallium/drivers/crocus/crocus_program.c +++ b/src/gallium/drivers/crocus/crocus_program.c @@ -2709,7 +2709,8 @@ crocus_create_uncompiled_shader(struct pipe_context *ctx, else ish->needs_edge_flag = false; - brw_preprocess_nir(screen->compiler, nir, NULL); + struct brw_nir_compiler_opts opts = {}; + brw_preprocess_nir(screen->compiler, nir, &opts); NIR_PASS_V(nir, brw_nir_lower_storage_image, devinfo); NIR_PASS_V(nir, crocus_lower_storage_image_derefs); diff --git a/src/gallium/drivers/iris/iris_program.c b/src/gallium/drivers/iris/iris_program.c index c87c121..4df3b87 100644 --- a/src/gallium/drivers/iris/iris_program.c +++ b/src/gallium/drivers/iris/iris_program.c @@ -2940,7 +2940,8 @@ iris_finalize_nir(struct pipe_screen *_screen, void *nirptr) NIR_PASS_V(nir, iris_fix_edge_flags); - brw_preprocess_nir(screen->compiler, nir, NULL); + struct brw_nir_compiler_opts opts = {}; + brw_preprocess_nir(screen->compiler, nir, &opts); NIR_PASS_V(nir, brw_nir_lower_storage_image, devinfo); NIR_PASS_V(nir, iris_lower_storage_image_derefs); diff --git a/src/intel/blorp/blorp.c b/src/intel/blorp/blorp.c index 23b75a7..245baaa 100644 --- a/src/intel/blorp/blorp.c +++ b/src/intel/blorp/blorp.c @@ -287,7 +287,8 @@ blorp_compile_fs(struct blorp_context *blorp, void *mem_ctx, wm_prog_data->base.nr_params = 0; wm_prog_data->base.param = NULL; - brw_preprocess_nir(compiler, nir, NULL); + struct brw_nir_compiler_opts opts = {}; + brw_preprocess_nir(compiler, nir, &opts); nir_remove_dead_variables(nir, nir_var_shader_in, NULL); nir_shader_gather_info(nir, nir_shader_get_entrypoint(nir)); @@ -321,7 +322,8 @@ blorp_compile_vs(struct blorp_context *blorp, void *mem_ctx, nir->options = compiler->nir_options[MESA_SHADER_VERTEX]; - brw_preprocess_nir(compiler, nir, NULL); + struct brw_nir_compiler_opts opts = {}; + brw_preprocess_nir(compiler, nir, &opts); nir_shader_gather_info(nir, nir_shader_get_entrypoint(nir)); vs_prog_data->inputs_read = nir->info.inputs_read; @@ -358,7 +360,8 @@ blorp_compile_cs(struct blorp_context *blorp, void *mem_ctx, memset(cs_prog_data, 0, sizeof(*cs_prog_data)); - brw_preprocess_nir(compiler, nir, NULL); + struct brw_nir_compiler_opts opts = {}; + brw_preprocess_nir(compiler, nir, &opts); nir_shader_gather_info(nir, nir_shader_get_entrypoint(nir)); NIR_PASS_V(nir, nir_lower_io, nir_var_uniform, type_size_scalar_bytes, diff --git a/src/intel/compiler/brw_kernel.c b/src/intel/compiler/brw_kernel.c index 59450a7..84a6771 100644 --- a/src/intel/compiler/brw_kernel.c +++ b/src/intel/compiler/brw_kernel.c @@ -367,7 +367,8 @@ brw_kernel_from_spirv(struct brw_compiler *compiler, nir_var_mem_shared | nir_var_mem_global, glsl_get_cl_type_size_align); - brw_preprocess_nir(compiler, nir, NULL); + struct brw_nir_compiler_opts opts = {}; + brw_preprocess_nir(compiler, nir, &opts); int max_arg_idx = -1; nir_foreach_uniform_variable(var, nir) { diff --git a/src/intel/compiler/brw_nir.c b/src/intel/compiler/brw_nir.c index 1933c48..1fbd150 100644 --- a/src/intel/compiler/brw_nir.c +++ b/src/intel/compiler/brw_nir.c @@ -900,7 +900,7 @@ lower_xehp_tg4_offset_filter(const nir_instr *instr, UNUSED const void *data) */ void brw_preprocess_nir(const struct brw_compiler *compiler, nir_shader *nir, - const nir_shader *softfp64) + const struct brw_nir_compiler_opts *opts) { const struct intel_device_info *devinfo = compiler->devinfo; UNUSED bool progress; /* Written by OPT */ @@ -921,7 +921,13 @@ brw_preprocess_nir(const struct brw_compiler *compiler, nir_shader *nir, !(devinfo->ver >= 10 || devinfo->platform == INTEL_PLATFORM_KBL)) OPT(brw_nir_apply_trig_workarounds); - if (devinfo->ver >= 12) + /* This workaround existing for performance reasons. Since it requires not + * setting RENDER_SURFACE_STATE::SurfaceArray when the array length is 1, + * we're loosing the HW robustness feature in that case. + * + * So when robust image access is enabled, just avoid the workaround. + */ + if (devinfo->ver >= 12 && !opts->robust_image_access) OPT(brw_nir_clamp_image_1d_2d_array_sizes); const nir_lower_tex_options tex_options = { @@ -951,10 +957,11 @@ brw_preprocess_nir(const struct brw_compiler *compiler, nir_shader *nir, brw_nir_optimize(nir, compiler, is_scalar, true); - OPT(nir_lower_doubles, softfp64, nir->options->lower_doubles_options); + OPT(nir_lower_doubles, opts->softfp64, nir->options->lower_doubles_options); if (OPT(nir_lower_int64)) { OPT(nir_opt_algebraic); - OPT(nir_lower_doubles, softfp64, nir->options->lower_doubles_options); + OPT(nir_lower_doubles, opts->softfp64, + nir->options->lower_doubles_options); } OPT(nir_lower_bit_size, lower_bit_size_callback, (void *)compiler); @@ -1738,7 +1745,8 @@ brw_nir_create_passthrough_tcs(void *mem_ctx, const struct brw_compiler *compile nir_validate_shader(nir, "in brw_nir_create_passthrough_tcs"); - brw_preprocess_nir(compiler, nir, NULL); + struct brw_nir_compiler_opts opts = {}; + brw_preprocess_nir(compiler, nir, &opts); return nir; } diff --git a/src/intel/compiler/brw_nir.h b/src/intel/compiler/brw_nir.h index 5d70575..c07126a 100644 --- a/src/intel/compiler/brw_nir.h +++ b/src/intel/compiler/brw_nir.h @@ -92,9 +92,17 @@ enum { void brw_nir_analyze_boolean_resolves(nir_shader *nir); +struct brw_nir_compiler_opts { + /* Soft floating point implementation shader */ + const nir_shader *softfp64; + + /* Whether robust image access is enabled */ + bool robust_image_access; +}; + void brw_preprocess_nir(const struct brw_compiler *compiler, nir_shader *nir, - const nir_shader *softfp64); + const struct brw_nir_compiler_opts *opts); void brw_nir_link_shaders(const struct brw_compiler *compiler, diff --git a/src/intel/compiler/brw_nir_rt.c b/src/intel/compiler/brw_nir_rt.c index 0c67e14..9ddfa71 100644 --- a/src/intel/compiler/brw_nir_rt.c +++ b/src/intel/compiler/brw_nir_rt.c @@ -501,7 +501,9 @@ brw_nir_create_raygen_trampoline(const struct brw_compiler *compiler, nir_shader *nir = b.shader; nir->info.name = ralloc_strdup(nir, "RT: TraceRay trampoline"); nir_validate_shader(nir, "in brw_nir_create_raygen_trampoline"); - brw_preprocess_nir(compiler, nir, NULL); + + struct brw_nir_compiler_opts opts = {}; + brw_preprocess_nir(compiler, nir, &opts); NIR_PASS_V(nir, brw_nir_lower_rt_intrinsics, devinfo); diff --git a/src/intel/vulkan/anv_pipeline.c b/src/intel/vulkan/anv_pipeline.c index bb0a31c..6d77168 100644 --- a/src/intel/vulkan/anv_pipeline.c +++ b/src/intel/vulkan/anv_pipeline.c @@ -222,7 +222,10 @@ anv_shader_stage_to_nir(struct anv_device *device, /* Vulkan uses the separate-shader linking model */ nir->info.separate_shader = true; - brw_preprocess_nir(compiler, nir, device->fp64_nir); + struct brw_nir_compiler_opts opts = { + .softfp64 = device->fp64_nir, + }; + brw_preprocess_nir(compiler, nir, &opts); if (nir->info.stage == MESA_SHADER_MESH && !nir->info.mesh.nv) { bool progress = false; diff --git a/src/intel/vulkan_hasvk/anv_pipeline.c b/src/intel/vulkan_hasvk/anv_pipeline.c index 778ee0f..5331625 100644 --- a/src/intel/vulkan_hasvk/anv_pipeline.c +++ b/src/intel/vulkan_hasvk/anv_pipeline.c @@ -160,7 +160,9 @@ anv_shader_stage_to_nir(struct anv_device *device, /* Vulkan uses the separate-shader linking model */ nir->info.separate_shader = true; - brw_preprocess_nir(compiler, nir, NULL); + struct brw_nir_compiler_opts opts = {}; + + brw_preprocess_nir(compiler, nir, &opts); return nir; }