From: Mikhail Skvortcov <m.skvortcov@partner.samsung.com>
Date: Tue, 23 May 2017 13:25:07 +0000 (+0300)
Subject: Adapt shared genLeaInstruction for arm32
X-Git-Tag: submit/tizen/20210909.063632~11030^2~6925^2~546^2~3
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=94a5609cec4921be1ff34ab5b6e85c705e19c5a2;p=platform%2Fupstream%2Fdotnet%2Fruntime.git

Adapt shared genLeaInstruction for arm32


Commit migrated from https://github.com/dotnet/coreclr/commit/eef101ffeabd39d45240c7a12a6449f386ae3abd
---

diff --git a/src/coreclr/src/jit/codegenarmarch.cpp b/src/coreclr/src/jit/codegenarmarch.cpp
index 48e0911..192d08e 100644
--- a/src/coreclr/src/jit/codegenarmarch.cpp
+++ b/src/coreclr/src/jit/codegenarmarch.cpp
@@ -2656,7 +2656,25 @@ void CodeGen::genCodeForStoreBlk(GenTreeBlk* blkOp)
     }
 }
 
-// produce code for a GT_LEA subnode
+//------------------------------------------------------------------------
+// genScaledAdd: A helper for genLeaInstruction.
+//
+void CodeGen::genScaledAdd(emitAttr attr, regNumber targetReg, regNumber baseReg, regNumber indexReg, int scale)
+{
+    emitter* emit = getEmitter();
+#if defined(_TARGET_ARM_)
+    emit->emitIns_R_R_R_I(INS_add, attr, targetReg, baseReg, indexReg, scale, INS_FLAGS_DONT_CARE, INS_OPTS_LSL);
+#elif defined(_TARGET_ARM64_)
+    emit->emitIns_R_R_R_I(INS_add, attr, targetReg, baseReg, indexReg, scale, INS_OPTS_LSL);
+#endif
+}
+
+//------------------------------------------------------------------------
+// genLeaInstruction: Produce code for a GT_LEA node.
+//
+// Arguments:
+//    lea - the node
+//
 void CodeGen::genLeaInstruction(GenTreeAddrMode* lea)
 {
     genConsumeOperands(lea);
@@ -2664,7 +2682,7 @@ void CodeGen::genLeaInstruction(GenTreeAddrMode* lea)
     emitAttr size   = emitTypeSize(lea);
     unsigned offset = lea->gtOffset;
 
-    // In ARM64 we can only load addresses of the form:
+    // In ARM we can only load addresses of the form:
     //
     // [Base + index*scale]
     // [Base + Offset]
@@ -2695,12 +2713,12 @@ void CodeGen::genLeaInstruction(GenTreeAddrMode* lea)
         {
             regNumber tmpReg = lea->GetSingleTempReg();
 
-            if (emitter::emitIns_valid_imm_for_add(offset, EA_8BYTE))
+            if (emitter::emitIns_valid_imm_for_add(offset))
             {
                 if (lsl > 0)
                 {
                     // Generate code to set tmpReg = base + index*scale
-                    emit->emitIns_R_R_R_I(INS_add, size, tmpReg, memBase->gtRegNum, index->gtRegNum, lsl, INS_OPTS_LSL);
+                    genScaledAdd(size, tmpReg, memBase->gtRegNum, index->gtRegNum, lsl);
                 }
                 else // no scale
                 {
@@ -2722,7 +2740,7 @@ void CodeGen::genLeaInstruction(GenTreeAddrMode* lea)
                 noway_assert(tmpReg != index->gtRegNum);
 
                 // Then compute target reg from [tmpReg + index*scale]
-                emit->emitIns_R_R_R_I(INS_add, size, lea->gtRegNum, tmpReg, index->gtRegNum, lsl, INS_OPTS_LSL);
+                genScaledAdd(size, lea->gtRegNum, tmpReg, index->gtRegNum, lsl);
             }
         }
         else
@@ -2730,8 +2748,7 @@ void CodeGen::genLeaInstruction(GenTreeAddrMode* lea)
             if (lsl > 0)
             {
                 // Then compute target reg from [base + index*scale]
-                emit->emitIns_R_R_R_I(INS_add, size, lea->gtRegNum, memBase->gtRegNum, index->gtRegNum, lsl,
-                                      INS_OPTS_LSL);
+                genScaledAdd(size, lea->gtRegNum, memBase->gtRegNum, index->gtRegNum, lsl);
             }
             else
             {
@@ -2744,7 +2761,7 @@ void CodeGen::genLeaInstruction(GenTreeAddrMode* lea)
     {
         GenTree* memBase = lea->Base();
 
-        if (emitter::emitIns_valid_imm_for_add(offset, EA_8BYTE))
+        if (emitter::emitIns_valid_imm_for_add(offset))
         {
             if (offset != 0)
             {
diff --git a/src/coreclr/src/jit/codegenlinear.h b/src/coreclr/src/jit/codegenlinear.h
index 59763bc5..994fc55 100644
--- a/src/coreclr/src/jit/codegenlinear.h
+++ b/src/coreclr/src/jit/codegenlinear.h
@@ -24,6 +24,10 @@ void genCodeForMulHi(GenTreeOp* treeNode);
 void genLeaInstruction(GenTreeAddrMode* lea);
 void genSetRegToCond(regNumber dstReg, GenTreePtr tree);
 
+#if defined(_TARGET_ARMARCH_)
+void genScaledAdd(emitAttr attr, regNumber targetReg, regNumber baseReg, regNumber indexReg, int scale);
+#endif // _TARGET_ARMARCH_
+
 #if defined(_TARGET_ARM_)
 void genCodeForMulLong(GenTreeMulLong* treeNode);
 #endif // _TARGET_ARM_
diff --git a/src/coreclr/src/jit/emitarm.h b/src/coreclr/src/jit/emitarm.h
index 1e286e8..dc8c28e 100644
--- a/src/coreclr/src/jit/emitarm.h
+++ b/src/coreclr/src/jit/emitarm.h
@@ -247,7 +247,7 @@ public:
 static bool emitIns_valid_imm_for_alu(int imm);
 static bool emitIns_valid_imm_for_mov(int imm);
 static bool emitIns_valid_imm_for_small_mov(regNumber reg, int imm, insFlags flags);
-static bool emitIns_valid_imm_for_add(int imm, insFlags flags);
+static bool emitIns_valid_imm_for_add(int imm, insFlags flags = INS_FLAGS_DONT_CARE);
 static bool emitIns_valid_imm_for_cmp(int imm, insFlags flags);
 static bool emitIns_valid_imm_for_add_sp(int imm);
 static bool emitIns_valid_imm_for_ldst_offset(int imm, emitAttr size);
diff --git a/src/coreclr/src/jit/emitarm64.h b/src/coreclr/src/jit/emitarm64.h
index 09158fb..ebebf51 100644
--- a/src/coreclr/src/jit/emitarm64.h
+++ b/src/coreclr/src/jit/emitarm64.h
@@ -464,7 +464,7 @@ static bool emitIns_valid_imm_for_movi(INT64 imm, emitAttr size);
 static bool emitIns_valid_imm_for_fmov(double immDbl);
 
 // true if this 'imm' can be encoded as a input operand to an add instruction
-static bool emitIns_valid_imm_for_add(INT64 imm, emitAttr size);
+static bool emitIns_valid_imm_for_add(INT64 imm, emitAttr size = EA_8BYTE);
 
 // true if this 'imm' can be encoded as a input operand to a cmp instruction
 static bool emitIns_valid_imm_for_cmp(INT64 imm, emitAttr size);