From: Sean Anderson Date: Wed, 24 Jun 2020 10:41:17 +0000 (-0400) Subject: riscv: Clear pending interrupts before enabling IPIs X-Git-Tag: v2020.10~139^2~2^2~12 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=9472630337e7c4ac442066b5a752aaa8c3b4d4a6;p=platform%2Fkernel%2Fu-boot.git riscv: Clear pending interrupts before enabling IPIs On some platforms (k210), the previous stage bootloader may have not cleared pending IPIs before transferring control to U-Boot. This can cause race conditions, as multiple harts all attempt to initialize the IPI controller at once. This patch clears IPIs before enabling them, ensuring that only one hart modifies shared memory at once. Signed-off-by: Sean Anderson Reviewed-by: Rick Chen --- diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S index 5f1c220..f408e41 100644 --- a/arch/riscv/cpu/start.S +++ b/arch/riscv/cpu/start.S @@ -65,6 +65,8 @@ _start: #else li t0, SIE_SSIE #endif + /* Clear any pending IPIs */ + csrc MODE_PREFIX(ip), t0 csrs MODE_PREFIX(ie), t0 #endif