From: Zhenyu Wang <zhenyuw@linux.intel.com>
Date: Sat, 22 Oct 2016 05:21:45 +0000 (+0800)
Subject: drm/i915/gvt: Fix broken mocs offset
X-Git-Tag: v5.15~11060^2~37^2~1051^2~11
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=946260e5fb60fcf3a4fbe77840280b5191300564;p=platform%2Fkernel%2Flinux-starfive.git

drm/i915/gvt: Fix broken mocs offset

Fix missed mocs offset reg setting for save/restore function.

Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
---

diff --git a/drivers/gpu/drm/i915/gvt/render.c b/drivers/gpu/drm/i915/gvt/render.c
index be1a7df..3af894b 100644
--- a/drivers/gpu/drm/i915/gvt/render.c
+++ b/drivers/gpu/drm/i915/gvt/render.c
@@ -177,6 +177,7 @@ static void load_mocs(struct intel_vgpu *vgpu, int ring_id)
 	if (!IS_SKYLAKE(dev_priv))
 		return;
 
+	offset.reg = regs[ring_id];
 	for (i = 0; i < 64; i++) {
 		gen9_render_mocs[ring_id][i] = I915_READ(offset);
 		I915_WRITE(offset, vgpu_vreg(vgpu, offset));
@@ -214,6 +215,7 @@ static void restore_mocs(struct intel_vgpu *vgpu, int ring_id)
 	if (!IS_SKYLAKE(dev_priv))
 		return;
 
+	offset.reg = regs[ring_id];
 	for (i = 0; i < 64; i++) {
 		vgpu_vreg(vgpu, offset) = I915_READ(offset);
 		I915_WRITE(offset, gen9_render_mocs[ring_id][i]);