From: Nick Clifton Date: Thu, 19 Nov 2009 14:07:11 +0000 (+0000) Subject: PR binutils/10924 X-Git-Tag: cgen-snapshot-20091201~101 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=945ee43039cf180d2b6b77b0d72953af50359d72;p=platform%2Fupstream%2Fbinutils.git PR binutils/10924 * gas/arm/arch4t-eabi.d: Restore previous expected dissambly of instructions using Immediate Offset addressing with an offset of zero. * gas/arm/arch4t.d: Likewise. * gas/arm/arm7t.d: Likewise. * gas/arm/xscale.d: Likewise. * gas/arm/wince-inst.d: Remove 'p' suffix from cmp, cmn, teq and tst instructions. PR binutils/10924 * arm-dis.c (print_insn_arm): Do not print an offset of zero when decoding Immediaate Offset addressing. --- diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog index b9de1d8..de0c6ca 100644 --- a/gas/testsuite/ChangeLog +++ b/gas/testsuite/ChangeLog @@ -1,3 +1,15 @@ +2009-11-19 Nick Clifton + + PR binutils/10924 + * gas/arm/arch4t-eabi.d: Restore previous expected dissambly of + instructions using Immediate Offset addressing with an offset of + zero. + * gas/arm/arch4t.d: Likewise. + * gas/arm/arm7t.d: Likewise. + * gas/arm/xscale.d: Likewise. + * gas/arm/wince-inst.d: Remove 'p' suffix from cmp, cmn, teq and + tst instructions. + 2009-11-18 Sebastian Pop * gas/i386/x86-64-xop.d: Update patterns. diff --git a/gas/testsuite/gas/arm/arch4t-eabi.d b/gas/testsuite/gas/arm/arch4t-eabi.d index 959770b..afd92f7 100644 --- a/gas/testsuite/gas/arm/arch4t-eabi.d +++ b/gas/testsuite/gas/arm/arch4t-eabi.d @@ -12,7 +12,7 @@ Disassembly of section .text: 0+04 <[^>]+> 012fff11 ? bxeq r1 .*: R_ARM_V4BX.* 0+08 <[^>]+> e15f30b8 ? ldrh r3, \[pc, #-8\] ; 0+08 <[^>]+> -0+0c <[^>]+> e1d540f0 ? ldrsh r4, \[r5, #0\] +0+0c <[^>]+> e1d540f0 ? ldrsh r4, \[r5\] 0+10 <[^>]+> e19140d3 ? ldrsb r4, \[r1, r3\] 0+14 <[^>]+> e1b410f4 ? ldrsh r1, \[r4, r4\]! 0+18 <[^>]+> 011510d3 ? ldrsbeq r1, \[r5, -r3\] @@ -22,7 +22,7 @@ Disassembly of section .text: 0+28 <[^>]+> e1541ffa ? ldrsh r1, \[r4, #-250\].* 0+2c <[^>]+> e1d51fd0 ? ldrsb r1, \[r5, #240\].* 0+30 <[^>]+> e1cf23b0 ? strh r2, \[pc, #48\] ; 0+68 <[^>]+> -0+34 <[^>]+> 11c330b0 ? strhne r3, \[r3, #0\] +0+34 <[^>]+> 11c330b0 ? strhne r3, \[r3\] 0+38 <[^>]+> e328f002 ? msr CPSR_f, #2 0+3c <[^>]+> e121f003 ? msr CPSR_c, r3 0+40 <[^>]+> e122f004 ? msr CPSR_x, r4 diff --git a/gas/testsuite/gas/arm/arch4t.d b/gas/testsuite/gas/arm/arch4t.d index dd979cd..6655852 100644 --- a/gas/testsuite/gas/arm/arch4t.d +++ b/gas/testsuite/gas/arm/arch4t.d @@ -10,7 +10,7 @@ Disassembly of section .text: 0+00 <[^>]+> e12fff10 ? bx r0 0+04 <[^>]+> 012fff11 ? bxeq r1 0+08 <[^>]+> e15f30b8 ? ldrh r3, \[pc, #-8\] ; 0+08 <[^>]+> -0+0c <[^>]+> e1d540f0 ? ldrsh r4, \[r5, #0\] +0+0c <[^>]+> e1d540f0 ? ldrsh r4, \[r5\] 0+10 <[^>]+> e19140d3 ? ldrsb r4, \[r1, r3\] 0+14 <[^>]+> e1b410f4 ? ldrsh r1, \[r4, r4\]! 0+18 <[^>]+> 011510d3 ? ldrsbeq r1, \[r5, -r3\] @@ -20,7 +20,7 @@ Disassembly of section .text: 0+28 <[^>]+> e1541ffa ? ldrsh r1, \[r4, #-250\].* 0+2c <[^>]+> e1d51fd0 ? ldrsb r1, \[r5, #240\].* 0+30 <[^>]+> e1cf23b0 ? strh r2, \[pc, #48\] ; 0+68 <[^>]+> -0+34 <[^>]+> 11c330b0 ? strhne r3, \[r3, #0\] +0+34 <[^>]+> 11c330b0 ? strhne r3, \[r3\] 0+38 <[^>]+> e328f002 ? msr CPSR_f, #2 0+3c <[^>]+> e121f003 ? msr CPSR_c, r3 0+40 <[^>]+> e122f004 ? msr CPSR_x, r4 diff --git a/gas/testsuite/gas/arm/arm7t.d b/gas/testsuite/gas/arm/arm7t.d index 4d1ca3c..a16192b 100644 --- a/gas/testsuite/gas/arm/arm7t.d +++ b/gas/testsuite/gas/arm/arm7t.d @@ -7,7 +7,7 @@ .*: +file format .*arm.* Disassembly of section .text: -0+00 <[^>]*> e1d100b0 ? ldrh r0, \[r1, #0\] +0+00 <[^>]*> e1d100b0 ? ldrh r0, \[r1\] 0+04 <[^>]*> e1f100b0 ? ldrh r0, \[r1, #0\]! 0+08 <[^>]*> e19100b2 ? ldrh r0, \[r1, r2\] 0+0c <[^>]*> e1b100b2 ? ldrh r0, \[r1, r2\]! @@ -18,7 +18,7 @@ Disassembly of section .text: 0+20 <[^>]*> e3a00cff ? mov r0, #65280 ; 0xff00 0+24 <[^>]*> e1df0bb4 ? ldrh r0, \[pc, #180\] ; 0+e0 <[^>]*> 0+28 <[^>]*> e1df0abc ? ldrh r0, \[pc, #172\] ; 0+dc <[^>]*> -0+2c <[^>]*> e1c100b0 ? strh r0, \[r1, #0\] +0+2c <[^>]*> e1c100b0 ? strh r0, \[r1\] 0+30 <[^>]*> e1e100b0 ? strh r0, \[r1, #0\]! 0+34 <[^>]*> e18100b2 ? strh r0, \[r1, r2\] 0+38 <[^>]*> e1a100b2 ? strh r0, \[r1, r2\]! @@ -27,7 +27,7 @@ Disassembly of section .text: 0+44 <[^>]*> e14100bc ? strh r0, \[r1, #-12\] 0+48 <[^>]*> e08100b2 ? strh r0, \[r1\], r2 0+4c <[^>]*> e1cf08b8 ? strh r0, \[pc, #136\] ; 0+dc <[^>]*> -0+50 <[^>]*> e1d100d0 ? ldrsb r0, \[r1, #0\] +0+50 <[^>]*> e1d100d0 ? ldrsb r0, \[r1\] 0+54 <[^>]*> e1f100d0 ? ldrsb r0, \[r1, #0\]! 0+58 <[^>]*> e19100d2 ? ldrsb r0, \[r1, r2\] 0+5c <[^>]*> e1b100d2 ? ldrsb r0, \[r1, r2\]! @@ -37,7 +37,7 @@ Disassembly of section .text: 0+6c <[^>]*> e09100d2 ? ldrsb r0, \[r1\], r2 0+70 <[^>]*> e3a000de ? mov r0, #222 ; 0xde 0+74 <[^>]*> e1df06d0 ? ldrsb r0, \[pc, #96\] ; 0+dc <[^>]*> -0+78 <[^>]*> e1d100f0 ? ldrsh r0, \[r1, #0\] +0+78 <[^>]*> e1d100f0 ? ldrsh r0, \[r1\] 0+7c <[^>]*> e1f100f0 ? ldrsh r0, \[r1, #0\]! 0+80 <[^>]*> e19100f2 ? ldrsh r0, \[r1, r2\] 0+84 <[^>]*> e1b100f2 ? ldrsh r0, \[r1, r2\]! diff --git a/gas/testsuite/gas/arm/armv1.d b/gas/testsuite/gas/arm/armv1.d index 99e8471..7899df7 100644 --- a/gas/testsuite/gas/arm/armv1.d +++ b/gas/testsuite/gas/arm/armv1.d @@ -30,16 +30,16 @@ Disassembly of section .text: 0+4c <[^>]*> e1d00000 ? bics r0, r0, r0 0+50 <[^>]*> e1100000 ? tst r0, r0 0+54 <[^>]*> e1100000 ? tst r0, r0 -0+58 <[^>]*> e110f000 ? tstp r0, r0 +0+58 <[^>]*> e110f000 ? tst r0, r0 0+5c <[^>]*> e1300000 ? teq r0, r0 0+60 <[^>]*> e1300000 ? teq r0, r0 -0+64 <[^>]*> e130f000 ? teqp r0, r0 +0+64 <[^>]*> e130f000 ? teq r0, r0 0+68 <[^>]*> e1500000 ? cmp r0, r0 0+6c <[^>]*> e1500000 ? cmp r0, r0 -0+70 <[^>]*> e150f000 ? cmpp r0, r0 +0+70 <[^>]*> e150f000 ? cmp r0, r0 0+74 <[^>]*> e1700000 ? cmn r0, r0 0+78 <[^>]*> e1700000 ? cmn r0, r0 -0+7c <[^>]*> e170f000 ? cmnp r0, r0 +0+7c <[^>]*> e170f000 ? cmn r0, r0 0+80 <[^>]*> e1a00000 ? nop[ ]+\(mov r0,r0\) 0+84 <[^>]*> e1b00000 ? movs r0, r0 0+88 <[^>]*> e1e00000 ? mvn r0, r0 diff --git a/gas/testsuite/gas/arm/wince_inst.d b/gas/testsuite/gas/arm/wince_inst.d index 5c14582..5b48966 100644 --- a/gas/testsuite/gas/arm/wince_inst.d +++ b/gas/testsuite/gas/arm/wince_inst.d @@ -97,22 +97,22 @@ Disassembly of section .text: 0+14c <[^>]*> e1720004 ? cmn r2, r4 0+150 <[^>]*> e1750287 ? cmn r5, r7, lsl #5 0+154 <[^>]*> e1710113 ? cmn r1, r3, lsl r1 -0+158 <[^>]*> e330f00a ? teqp r0, #10 -0+15c <[^>]*> e132f004 ? teqp r2, r4 -0+160 <[^>]*> e135f287 ? teqp r5, r7, lsl #5 -0+164 <[^>]*> e131f113 ? teqp r1, r3, lsl r1 -0+168 <[^>]*> e370f00a ? cmnp r0, #10 -0+16c <[^>]*> e172f004 ? cmnp r2, r4 -0+170 <[^>]*> e175f287 ? cmnp r5, r7, lsl #5 -0+174 <[^>]*> e171f113 ? cmnp r1, r3, lsl r1 -0+178 <[^>]*> e350f00a ? cmpp r0, #10 -0+17c <[^>]*> e152f004 ? cmpp r2, r4 -0+180 <[^>]*> e155f287 ? cmpp r5, r7, lsl #5 -0+184 <[^>]*> e151f113 ? cmpp r1, r3, lsl r1 -0+188 <[^>]*> e310f00a ? tstp r0, #10 -0+18c <[^>]*> e112f004 ? tstp r2, r4 -0+190 <[^>]*> e115f287 ? tstp r5, r7, lsl #5 -0+194 <[^>]*> e111f113 ? tstp r1, r3, lsl r1 +0+158 <[^>]*> e330f00a ? teq r0, #10 +0+15c <[^>]*> e132f004 ? teq r2, r4 +0+160 <[^>]*> e135f287 ? teq r5, r7, lsl #5 +0+164 <[^>]*> e131f113 ? teq r1, r3, lsl r1 +0+168 <[^>]*> e370f00a ? cmn r0, #10 +0+16c <[^>]*> e172f004 ? cmn r2, r4 +0+170 <[^>]*> e175f287 ? cmn r5, r7, lsl #5 +0+174 <[^>]*> e171f113 ? cmn r1, r3, lsl r1 +0+178 <[^>]*> e350f00a ? cmp r0, #10 +0+17c <[^>]*> e152f004 ? cmp r2, r4 +0+180 <[^>]*> e155f287 ? cmp r5, r7, lsl #5 +0+184 <[^>]*> e151f113 ? cmp r1, r3, lsl r1 +0+188 <[^>]*> e310f00a ? tst r0, #10 +0+18c <[^>]*> e112f004 ? tst r2, r4 +0+190 <[^>]*> e115f287 ? tst r5, r7, lsl #5 +0+194 <[^>]*> e111f113 ? tst r1, r3, lsl r1 0+198 <[^>]*> e0000291 ? mul r0, r1, r2 0+19c <[^>]*> e0110392 ? muls r1, r2, r3 0+1a0 <[^>]*> 10000091 ? mulne r0, r1, r0 diff --git a/gas/testsuite/gas/arm/xscale.d b/gas/testsuite/gas/arm/xscale.d index 01056cd..da4d1d7 100644 --- a/gas/testsuite/gas/arm/xscale.d +++ b/gas/testsuite/gas/arm/xscale.d @@ -23,7 +23,7 @@ Disassembly of section .text: 0+34 <[^>]*> f5d1f789 pld \[r1, #1929\].* 0+38 <[^>]*> f7d2f003 pld \[r2, r3\] 0+3c <[^>]*> f754f285 pld \[r4, -r5, lsl #5\] -0+40 <[^>]*> e1c100d0 ldrd r0, \[r1, #0\] +0+40 <[^>]*> e1c100d0 ldrd r0, \[r1\] 0+44 <[^>]*> 01c327d8 ldrdeq r2, \[r3, #120\].* 0+48 <[^>]*> b10540d6 ldrdlt r4, \[r5, -r6\] 0+4c <[^>]*> e16a88f9 strd r8, \[sl, #-137\]!.* diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index accb7b9..ad09adc 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,9 @@ +2009-11-19 Nick Clifton + + PR binutils/10924 + * arm-dis.c (print_insn_arm): Do not print an offset of zero when + decoding Immediaate Offset addressing. + 2009-11-18 Sebastian Pop PR binutils/10973 diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c index e59cc6c..38e1b66 100644 --- a/opcodes/arm-dis.c +++ b/opcodes/arm-dis.c @@ -2871,7 +2871,10 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given) if (PRE_BIT_SET) { - func (stream, "[pc, #%d]\t; ", offset); + if (offset) + func (stream, "[pc, #%d]\t; ", offset); + else + func (stream, "[pc]\t; "); info->print_address_func (offset + pc + 8, info); } else @@ -2892,14 +2895,20 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given) if (PRE_BIT_SET) { - /* Pre-indexed. */ if (IMMEDIATE_BIT_SET) { - /* PR 10924: Offset must be printed, even if it is zero. */ - func (stream, ", #%d", offset); + if (WRITEBACK_BIT_SET) + /* Immediate Pre-indexed. */ + /* PR 10924: Offset must be printed, even if it is zero. */ + func (stream, ", #%d", offset); + else if (offset) + /* Immediate Offset: printing zero offset is optional. */ + func (stream, ", #%d", offset); + value_in_comment = offset; } - else /* Register. */ + else + /* Register Offset or Register Pre-Indexed. */ func (stream, ", %s%s", NEGATIVE_BIT_SET ? "-" : "", arm_regnames[given & 0xf]); @@ -2907,19 +2916,24 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given) func (stream, "]%s", WRITEBACK_BIT_SET ? "!" : ""); } - else /* Post-indexed. */ + else { if (IMMEDIATE_BIT_SET) { + /* Immediate Post-indexed. */ /* PR 10924: Offset must be printed, even if it is zero. */ func (stream, "], #%d", offset); value_in_comment = offset; } - else /* Register. */ + else + /* Register Post-indexed. */ func (stream, "], %s%s", NEGATIVE_BIT_SET ? "-" : "", arm_regnames[given & 0xf]); + /* Writeback is automatically implied by post- addressing. + Setting the W bit is unnecessary and ARM specify it as + being unpredictable. */ if (WRITEBACK_BIT_SET && ! allow_unpredictable) func (stream, UNPREDICTABLE_INSTRUCTION); }