From: Thierry Reding <treding@nvidia.com>
Date: Fri, 26 Jul 2019 10:16:18 +0000 (+0200)
Subject: arm64: tegra: Fix base address for SOR1 on Tegra194
X-Git-Tag: v5.15~4957^2~20^2~19
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=939e7430dee4e1c0595124b8ccd1c8b5db162dd8;p=platform%2Fkernel%2Flinux-starfive.git

arm64: tegra: Fix base address for SOR1 on Tegra194

The SOR1 hardware block's registers start at physical address 0x15b40000
as correctly specified by the unit-address, but the reg property lists a
wrong value, likely because it was copy-and-pasted from SOR0 but not
correctly updated.

Signed-off-by: Thierry Reding <treding@nvidia.com>
---

diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
index d15c4f0..a84a8b4 100644
--- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
@@ -1078,7 +1078,7 @@
 
 			sor1: sor@15b40000 {
 				compatible = "nvidia,tegra194-sor";
-				reg = <0x155c0000 0x40000>;
+				reg = <0x15b40000 0x40000>;
 				interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&bpmp TEGRA194_CLK_SOR1_REF>,
 					 <&bpmp TEGRA194_CLK_SOR1_OUT>,