From: Dave Airlie Date: Thu, 15 Feb 2018 23:36:04 +0000 (+1000) Subject: Merge tag 'topic/hdcp-2018-02-13' of git://anongit.freedesktop.org/drm/drm-misc into... X-Git-Tag: v4.19~1144^2~33 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=933519a5a269d8460450545adefcb5caec622cac;p=platform%2Fkernel%2Flinux-rpi3.git Merge tag 'topic/hdcp-2018-02-13' of git://anongit.freedesktop.org/drm/drm-misc into drm-next Add HDCP support to i915 drm driver. * tag 'topic/hdcp-2018-02-13' of git://anongit.freedesktop.org/drm/drm-misc: (26 commits) drm/i915: fix misalignment in HDCP register def drm/i915: Reauthenticate HDCP on failure drm/i915: Detect panel's hdcp capability drm/i915: Optimize HDCP key load drm/i915: Retry HDCP bksv read drm/i915: Connector info in HDCP debug msgs drm/i915: Stop encryption for repeater with no sink drm/i915: Handle failure from 2nd stage HDCP auth drm/i915: Downgrade hdcp logs from INFO to DEBUG_KMS drm/i915: Restore HDCP DRM_INFO when with no downstream drm/i915: Check for downstream topology errors drm/i915: Start repeater auth on READY/CP_IRQ drm/i915: II stage HDCP auth for repeater only drm/i915: Extending HDCP for HSW, BDW and BXT+ drm/i915/dp: Fix compilation of intel_dp_hdcp_check_link drm/i915: Only disable HDCP when it's active drm/i915: Don't allow HDCP on PORT E/F drm/i915: Implement HDCP for DisplayPort drm/i915: Implement HDCP for HDMI drm/i915: Add function to output Aksv over GMBUS ... --- 933519a5a269d8460450545adefcb5caec622cac diff --cc drivers/gpu/drm/i915/i915_reg.h index 1489dd3,800ef0c..e9c79b5 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@@ -8467,19 -8347,89 +8469,101 @@@ enum skl_power_gate #define SKL_PW_TO_PG(pw) ((pw) - SKL_DISP_PW_1 + SKL_PG1) #define SKL_FUSE_PG_DIST_STATUS(pg) (1 << (27 - (pg))) +#define _CNL_AUX_REG_IDX(pw) ((pw) - 9) +#define _CNL_AUX_ANAOVRD1_B 0x162250 +#define _CNL_AUX_ANAOVRD1_C 0x162210 +#define _CNL_AUX_ANAOVRD1_D 0x1622D0 +#define _CNL_AUX_ANAOVRD1_F 0x162A90 +#define CNL_AUX_ANAOVRD1(pw) _MMIO(_PICK(_CNL_AUX_REG_IDX(pw), \ + _CNL_AUX_ANAOVRD1_B, \ + _CNL_AUX_ANAOVRD1_C, \ + _CNL_AUX_ANAOVRD1_D, \ + _CNL_AUX_ANAOVRD1_F)) +#define CNL_AUX_ANAOVRD1_ENABLE (1<<16) +#define CNL_AUX_ANAOVRD1_LDO_BYPASS (1<<23) + /* HDCP Key Registers */ + #define HDCP_KEY_CONF _MMIO(0x66c00) + #define HDCP_AKSV_SEND_TRIGGER BIT(31) + #define HDCP_CLEAR_KEYS_TRIGGER BIT(30) + #define HDCP_KEY_LOAD_TRIGGER BIT(8) + #define HDCP_KEY_STATUS _MMIO(0x66c04) + #define HDCP_FUSE_IN_PROGRESS BIT(7) + #define HDCP_FUSE_ERROR BIT(6) + #define HDCP_FUSE_DONE BIT(5) + #define HDCP_KEY_LOAD_STATUS BIT(1) + #define HDCP_KEY_LOAD_DONE BIT(0) + #define HDCP_AKSV_LO _MMIO(0x66c10) + #define HDCP_AKSV_HI _MMIO(0x66c14) + + /* HDCP Repeater Registers */ + #define HDCP_REP_CTL _MMIO(0x66d00) + #define HDCP_DDIB_REP_PRESENT BIT(30) + #define HDCP_DDIA_REP_PRESENT BIT(29) + #define HDCP_DDIC_REP_PRESENT BIT(28) + #define HDCP_DDID_REP_PRESENT BIT(27) + #define HDCP_DDIF_REP_PRESENT BIT(26) + #define HDCP_DDIE_REP_PRESENT BIT(25) + #define HDCP_DDIB_SHA1_M0 (1 << 20) + #define HDCP_DDIA_SHA1_M0 (2 << 20) + #define HDCP_DDIC_SHA1_M0 (3 << 20) + #define HDCP_DDID_SHA1_M0 (4 << 20) + #define HDCP_DDIF_SHA1_M0 (5 << 20) + #define HDCP_DDIE_SHA1_M0 (6 << 20) /* Bspec says 5? */ + #define HDCP_SHA1_BUSY BIT(16) + #define HDCP_SHA1_READY BIT(17) + #define HDCP_SHA1_COMPLETE BIT(18) + #define HDCP_SHA1_V_MATCH BIT(19) + #define HDCP_SHA1_TEXT_32 (1 << 1) + #define HDCP_SHA1_COMPLETE_HASH (2 << 1) + #define HDCP_SHA1_TEXT_24 (4 << 1) + #define HDCP_SHA1_TEXT_16 (5 << 1) + #define HDCP_SHA1_TEXT_8 (6 << 1) + #define HDCP_SHA1_TEXT_0 (7 << 1) + #define HDCP_SHA_V_PRIME_H0 _MMIO(0x66d04) + #define HDCP_SHA_V_PRIME_H1 _MMIO(0x66d08) + #define HDCP_SHA_V_PRIME_H2 _MMIO(0x66d0C) + #define HDCP_SHA_V_PRIME_H3 _MMIO(0x66d10) + #define HDCP_SHA_V_PRIME_H4 _MMIO(0x66d14) + #define HDCP_SHA_V_PRIME(h) _MMIO((0x66d04 + h * 4)) + #define HDCP_SHA_TEXT _MMIO(0x66d18) + + /* HDCP Auth Registers */ + #define _PORTA_HDCP_AUTHENC 0x66800 + #define _PORTB_HDCP_AUTHENC 0x66500 + #define _PORTC_HDCP_AUTHENC 0x66600 + #define _PORTD_HDCP_AUTHENC 0x66700 + #define _PORTE_HDCP_AUTHENC 0x66A00 + #define _PORTF_HDCP_AUTHENC 0x66900 + #define _PORT_HDCP_AUTHENC(port, x) _MMIO(_PICK(port, \ + _PORTA_HDCP_AUTHENC, \ + _PORTB_HDCP_AUTHENC, \ + _PORTC_HDCP_AUTHENC, \ + _PORTD_HDCP_AUTHENC, \ + _PORTE_HDCP_AUTHENC, \ + _PORTF_HDCP_AUTHENC) + x) + #define PORT_HDCP_CONF(port) _PORT_HDCP_AUTHENC(port, 0x0) + #define HDCP_CONF_CAPTURE_AN BIT(0) + #define HDCP_CONF_AUTH_AND_ENC (BIT(1) | BIT(0)) + #define PORT_HDCP_ANINIT(port) _PORT_HDCP_AUTHENC(port, 0x4) + #define PORT_HDCP_ANLO(port) _PORT_HDCP_AUTHENC(port, 0x8) + #define PORT_HDCP_ANHI(port) _PORT_HDCP_AUTHENC(port, 0xC) + #define PORT_HDCP_BKSVLO(port) _PORT_HDCP_AUTHENC(port, 0x10) + #define PORT_HDCP_BKSVHI(port) _PORT_HDCP_AUTHENC(port, 0x14) + #define PORT_HDCP_RPRIME(port) _PORT_HDCP_AUTHENC(port, 0x18) + #define PORT_HDCP_STATUS(port) _PORT_HDCP_AUTHENC(port, 0x1C) + #define HDCP_STATUS_STREAM_A_ENC BIT(31) + #define HDCP_STATUS_STREAM_B_ENC BIT(30) + #define HDCP_STATUS_STREAM_C_ENC BIT(29) + #define HDCP_STATUS_STREAM_D_ENC BIT(28) + #define HDCP_STATUS_AUTH BIT(21) + #define HDCP_STATUS_ENC BIT(20) + #define HDCP_STATUS_RI_MATCH BIT(19) + #define HDCP_STATUS_R0_READY BIT(18) + #define HDCP_STATUS_AN_READY BIT(17) + #define HDCP_STATUS_CIPHER BIT(16) + #define HDCP_STATUS_FRAME_CNT(x) ((x >> 8) & 0xff) + /* Per-pipe DDI Function Control */ #define _TRANS_DDI_FUNC_CTL_A 0x60400 #define _TRANS_DDI_FUNC_CTL_B 0x61400 diff --cc drivers/gpu/drm/i915/intel_drv.h index cdcbeb5,c902be8..468ec1e --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@@ -1757,9 -1843,18 +1842,19 @@@ static inline void intel_backlight_devi } #endif /* CONFIG_BACKLIGHT_CLASS_DEVICE */ + /* intel_hdcp.c */ + void intel_hdcp_atomic_check(struct drm_connector *connector, + struct drm_connector_state *old_state, + struct drm_connector_state *new_state); + int intel_hdcp_init(struct intel_connector *connector, + const struct intel_hdcp_shim *hdcp_shim); + int intel_hdcp_enable(struct intel_connector *connector); + int intel_hdcp_disable(struct intel_connector *connector); + int intel_hdcp_check_link(struct intel_connector *connector); + bool is_hdcp_supported(struct drm_i915_private *dev_priv, enum port port); /* intel_psr.c */ +#define CAN_PSR(dev_priv) (HAS_PSR(dev_priv) && dev_priv->psr.sink_support) void intel_psr_enable(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state); void intel_psr_disable(struct intel_dp *intel_dp,